E. Strohmaier, J. J. Dongarra, H. W. Meuer, and H. D. Simon, The marketplace of high-performance computing, Parallel Computing, vol.25, issue.13-14, pp.1517-1544, 1999.
DOI : 10.1016/S0167-8191(99)00067-8

A. Gentile, D. Scott, and . Wills, Portable video supercomputing, IEEE Transactions on Computers, vol.53, issue.8, 2004.
DOI : 10.1109/TC.2004.48

W. C. Meilander, J. W. Baker, and M. Jin, Importance of SIMD computation reconsidered, Proceedings International Parallel and Distributed Processing Symposium, 2003.
DOI : 10.1109/IPDPS.2003.1213480

M. Baklouti, . Ph, J. Marquet, M. Dekeyser, and . Abid, A design and an implementation of a parallel based SIMD architecture for SoC on FPGA, Proceedings of Conference on Design and Architectures for Signal and Image processing (DASIP), 2008.

X. Xu, S. G. Ziavras, and T. G. Chang, An FPGA-Based Parallel Accelerator for Matrix Multiplications in the Newton-Raphson Method, Lecture Notes in Computer Science, Embedded and Ubiquitous Computing, pp.458-468, 2005.
DOI : 10.1007/11596356_47

C. Xiaoyi, Y. Qingdong, and L. Peng, Data Bypassing Architecture and Circuit Design for 32-bit Digital Signal Processor, Journal of Electronics, vol.22, issue.6, 2005.

M. Z. Hasan and S. G. Sotirios, Customized kernel execution on reconfigurable hardware for embedded applications, Microprocessors and Microsystems, vol.33, issue.3, p.211220, 2009.
DOI : 10.1016/j.micpro.2008.12.003

M. Sayed, W. Badawy, and G. Jullien, Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture, IEEE Transactions on Circuits and Systems II: Express Briefs, vol.55, issue.9, 2008.
DOI : 10.1109/TCSII.2008.923398

R. Lopez-rosas, A. De-luca, and F. Barbosa-santillan, SIMD Architecture for Image Segmentation using Sobel Operators Implemented in FPGA Technology, 2005 2nd International Conference on Electrical and Electronics Engineering, 2005.
DOI : 10.1109/ICEEE.2005.1529577

S. Connors, T. Brown, J. Hansen, and C. Kief, Mips source code, http://www.eece.unm.edu/ivpcl/classes/mips microprocessor/mips microprocessor .html. [16] Altera, Nios II Processor Reference Handbook, 2009.