An MDE approach for modeling network on chip topologies

Abstract : Network on Chip (NoC) is a research field path that primarily addresses the global communication in System on Chip (SoC).The selected topology of the components interconnects plays a prime role in the performance of NoC architecture, for NoC conception, high-level synthesis approaches are utilized thus the behaviorally description of the system is refined into an accurate register-transfer-level (RTL) design for SoC implementation. In the recent MARTE (Modeling and Analysis of Real-time and Embedded Systems) Profile, a notion of multidimensional multiplicity has been proposed to model repetitive structures and topology. This paper presents a contribution for a new methodology for modeling NoC based Model Driven Architecture and the Modeling and Analysis of Real-Time and embedded System (MARTE), it aims to prove the effectiveness of standard MARTE in modeling irregular or globally irregular locally regular architectures. We will start this work by high level abstraction to reach low level through generated VHDL code.
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Communication dans un congrès
Design and Technology of Integrated Systems in Nanoscale Era (DTIS), 2010 5th International Conference on, Mar 2010, Hammamet, Tunisia. 2010, 〈10.1109/DTIS.2010.5487596〉
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https://hal.inria.fr/inria-00526629
Contributeur : Mister Dart <>
Soumis le : vendredi 15 octobre 2010 - 11:34:08
Dernière modification le : jeudi 11 janvier 2018 - 01:49:31

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M. Elhaji, Pierre Boulet, S. Meftali, A. Zitouni, J. Dekeyser, et al.. An MDE approach for modeling network on chip topologies. Design and Technology of Integrated Systems in Nanoscale Era (DTIS), 2010 5th International Conference on, Mar 2010, Hammamet, Tunisia. 2010, 〈10.1109/DTIS.2010.5487596〉. 〈inria-00526629〉

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