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Conference papers

Towards Automatic Accuracy Validation and Optimization of Fixed-Point Hardware Descriptions in SystemC

Arnaud Tisserand 1
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Keywords : computer arithmetic fixed-point arithmetic operator accuracy rounding error integrated circuit hardware description language
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Conference papers
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https://hal.inria.fr/inria-00536554
Contributor : Arnaud Tisserand Connect in order to contact the contributor
Submitted on : Tuesday, November 16, 2010 - 2:07:16 PM
Last modification on : Tuesday, October 19, 2021 - 11:58:51 PM

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  • HAL Id : inria-00536554, version 1

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CNRS | INRIA | UNIV-RENNES1 | IRISA | IRISA-D3 | INSTITUT-TELECOM | UR1-MATH-STIC | UR1-UFR-ISTIC | UNIV-RENNES | UR1-MATH-NUM | INSA-RENNES | EC-PARIS

Citation

Arnaud Tisserand. Towards Automatic Accuracy Validation and Optimization of Fixed-Point Hardware Descriptions in SystemC. 14th GAMM-IMACS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics (SCAN), Sep 2010, Lyon, France. ⟨inria-00536554⟩

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