Towards Automatic Accuracy Validation and Optimization of Fixed-Point Hardware Descriptions in SystemC

Arnaud Tisserand 1
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Keywords : computer arithmetic fixed-point arithmetic operator accuracy rounding error integrated circuit hardware description language
Type de document :
Communication dans un congrès
14th GAMM-IMACS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics (SCAN), Sep 2010, Lyon, France. 2010
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https://hal.inria.fr/inria-00536554
Contributeur : Arnaud Tisserand <>
Soumis le : mardi 16 novembre 2010 - 14:07:16
Dernière modification le : mercredi 11 avril 2018 - 01:57:06

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  • HAL Id : inria-00536554, version 1

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INRIA | IRISA | IRISA-D3 | UR1-UFR-ISTIC | UNIV-RENNES | INRIA-RENGRE

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Arnaud Tisserand. Towards Automatic Accuracy Validation and Optimization of Fixed-Point Hardware Descriptions in SystemC. 14th GAMM-IMACS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics (SCAN), Sep 2010, Lyon, France. 2010. 〈inria-00536554〉

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