Task placement for dynamic and partial reconfigurable architecture - Archive ouverte HAL Access content directly
Conference Papers Year : 2010

Task placement for dynamic and partial reconfigurable architecture

Domains

Computer Science [cs] Hardware Architecture [cs.AR]

Sébastien Pillement  : Connect in order to contact the contributor

https://hal.inria.fr/inria-00536714

Submitted on : Tuesday, November 16, 2010-6:00:23 PM

Last modification on : Friday, March 24, 2023-2:52:53 PM

Not file

Dates and versions

inria-00536714 , version 1 (16-11-2010)

Identifiers

  • HAL Id : inria-00536714 , version 1

Cite

Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys. Task placement for dynamic and partial reconfigurable architecture. Conference on Design and Architectures for Signal and Image Processing, Oct 2010, Edimbourg, United Kingdom. ⟨inria-00536714⟩

Export

BibTeX TEI Dublin Core DC Terms EndNote Datacite

Collections

INSTITUT-TELECOM EC-PARIS UNIV-RENNES1 CNRS INRIA INSA-RENNES IRISA IRISA-D3 INRIA2 UR1-MATH-STIC UR1-UFR-ISTIC UNIV-RENNES UR1-MATH-NUM
207 View
0 Download

Share

Gmail Facebook Twitter LinkedIn More