Efficient implementation of Parallel BCD Multiplication in LUT-6 FPGAs

Alvaro Vazquez 1 Florent De Dinechin 1
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : Decimal multiplication is one of the most frequent operations used by many financial, business and user-oriented applications but current implementations in FPGAs are very inefficient in terms of both area and latency when compared to binary multipliers. In this paper we present a new method for implementing BCD multiplication more efficiently than previous proposals in current FPGA devices with 6-input LUTs. In particular, a combinational implementation maps quite well into the slice structure of the Xilinx Virtex-5/Virtex-6 families and it is highly pipelineable. The synthesis results for a Virtex-6 device indicate that our proposal outperforms the area and latency figures of previous implementations in FPGAs.
Document type :
Conference papers
2010 International Conference on Field-Programmable Technology, Dec 2010, Beijing, China. 2010
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https://hal.inria.fr/inria-00546028
Contributor : Alvaro Vazquez <>
Submitted on : Monday, December 13, 2010 - 3:11:26 PM
Last modification on : Thursday, October 19, 2017 - 1:12:43 AM

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  • HAL Id : inria-00546028, version 1

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Alvaro Vazquez, Florent De Dinechin. Efficient implementation of Parallel BCD Multiplication in LUT-6 FPGAs. 2010 International Conference on Field-Programmable Technology, Dec 2010, Beijing, China. 2010. 〈inria-00546028〉

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