System-Level Synthesis for Ultra Low-Power Wireless Sensor Nodes

Abstract : Engineering a hardware platform for a Wireless Sensor Network (WSN) node is known to be a tough challenge, as the design must enforce many severe constraints, among which energy dissipation is by far the most challenging one. Today, most of the WSN node platforms are based on low cost and low-power programmable micro controllers, even if it is acknowledged that their energy efficiency remains limited and hinders the wide-spreading of WSN to new applications. In this paper, we propose a complete system level flow for an alternative approach based on the concept of hardware micro-tasks, which relies on hardware specialization and power gating to dramatically improve the energy efficiency of the computational part of the node. Early estimates show power saving by more than one order of magnitude over MCU-based implementations.
Type de document :
Communication dans un congrès
Proc. of the 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD), Sep 2010, Lille, France, France. pp.493 - 500, 2010
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https://hal.inria.fr/inria-00554204
Contributeur : Steven Derrien <>
Soumis le : lundi 10 janvier 2011 - 14:41:35
Dernière modification le : mercredi 16 mai 2018 - 11:23:26

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  • HAL Id : inria-00554204, version 1

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Adeel Pasha, Steven Derrien, Olivier Sentieys. System-Level Synthesis for Ultra Low-Power Wireless Sensor Nodes. Proc. of the 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD), Sep 2010, Lille, France, France. pp.493 - 500, 2010. 〈inria-00554204〉

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