Logical Time @ Work for the Modeling and Analysis of Embedded Systems

Frédéric Mallet 1
1 AOSTE - Models and methods of analysis and optimization for systems with real-time and embedding constraints
CRISAM - Inria Sophia Antipolis - Méditerranée , Inria Paris-Rocquencourt, COMRED - COMmunications, Réseaux, systèmes Embarqués et Distribués
Abstract : Logical time is a relaxed form of time promoted by synchronous languages that is functional, elastic (can be abstracted or refined), and multiform. All these properties make logical time adequate also at design time, whereas precise physical time annotations should only matter in later post-synthesis stages. The Clock Constraint Specification Language (CCSL) is a concrete language dedicated to the modeling and analysis of logical time properties. CCSL was initially defined as a companion for the time model of the UML profile for MARTE. It has now become a full-fledged domain-specific modeling language for capturing causal, chronological and timed relationships. It should complement other syntactic models to capture their underlying model of computation. This book starts by describing the historical models of concurrency that have inspired the construction of CCSL. Then, CCSL is introduced and used to build libraries dedicated to two emerging standard models from the automotive (East-ADL) and the avionic (AADL) domains. Finally, an observer-based technique to verify Esterel and VHDL implementations against CCSL specifications is presented.
Type de document :
Ouvrage (y compris édition critique et traduction)
LAP LAMBERT Academic Publishing, pp.124, 2011, 978-3-8433-9388-1
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https://hal.inria.fr/inria-00561247
Contributeur : Frédéric Mallet <>
Soumis le : lundi 31 janvier 2011 - 19:13:06
Dernière modification le : lundi 4 décembre 2017 - 15:14:09

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  • HAL Id : inria-00561247, version 1

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Frédéric Mallet. Logical Time @ Work for the Modeling and Analysis of Embedded Systems. LAP LAMBERT Academic Publishing, pp.124, 2011, 978-3-8433-9388-1. 〈inria-00561247〉

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