(Pen)-ultimate tiling?

Abstract : In the framework of perfect loop nests with uniform dependences, tiling is a technique used to group elemental computation points so as to increase computation granularity and to reduce the overhead due to communication time. We review existing approaches from the literature, together with the optimization criteria that are used for determining a "good" or "optimal" tiling. Then we explain the need to introduce yet another criterion for defining "optimal tiling" in a scalable environment. Althoug hour criterion is more complex than previously used ones, we are able to prove a theorem on optimality, and to provide a constructive method for defining the "optimal tiling".
Type de document :
Article dans une revue
Integration, the VLSI Journal, Elsevier, 1994, 17, pp.33-51
Liste complète des métadonnées

https://hal.inria.fr/inria-00564996
Contributeur : Pierre Boulet <>
Soumis le : jeudi 10 février 2011 - 16:53:08
Dernière modification le : vendredi 20 avril 2018 - 15:44:24

Identifiants

  • HAL Id : inria-00564996, version 1

Collections

Citation

Pierre Boulet, Alain Darte, Tanguy Risset, Yves Robert. (Pen)-ultimate tiling?. Integration, the VLSI Journal, Elsevier, 1994, 17, pp.33-51. 〈inria-00564996〉

Partager

Métriques

Consultations de la notice

113