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Article Dans Une Revue Integration, the VLSI Journal Année : 1994

(Pen)-ultimate tiling?

Résumé

In the framework of perfect loop nests with uniform dependences, tiling is a technique used to group elemental computation points so as to increase computation granularity and to reduce the overhead due to communication time. We review existing approaches from the literature, together with the optimization criteria that are used for determining a "good" or "optimal" tiling. Then we explain the need to introduce yet another criterion for defining "optimal tiling" in a scalable environment. Althoug hour criterion is more complex than previously used ones, we are able to prove a theorem on optimality, and to provide a constructive method for defining the "optimal tiling".
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Dates et versions

inria-00564996 , version 1 (10-02-2011)

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  • HAL Id : inria-00564996 , version 1

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Pierre Boulet, Alain Darte, Tanguy Risset, Yves Robert. (Pen)-ultimate tiling?. Integration, the VLSI Journal, 1994, 17, pp.33-51. ⟨inria-00564996⟩
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