Modeling Networks-on-Chip at System Level with the MARTE UML profile

Majdi Elhaji 1 Pierre Boulet 2, * Rached Tourki 1 Abdelkrim Zitouni 1 Jean-Luc Dekeyser 2 Samy Meftali 2
* Auteur correspondant
2 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, Inria Lille - Nord Europe
Abstract : The study of Networks on Chips (NoCs) is a research field that primarily addresses the global communication in Systems-on-Chip (SoCs). The selected topology and the routing algorithm play a prime role in the performance of NoC architectures. In order to handle the design complexity and meet the tight time-to-market constraints, it is important to automate most of these NoC design phases. The extension of the UML language called UML profile for MARTE (Modeling and Analysis of Real-Time and Embedded systems) specifies some concepts for model-based design and analysis of real time and embedded systems. This paper presents a MARTE based methodology for modeling concepts of NoC based architectures. It aims at improving the effectiveness of the MARTE standard by clarifying some notations and extending some definitions in the standard, in order to be able to model complex architectures like NoCs.
Type de document :
Communication dans un congrès
M-BED'2011, Mar 2011, Grenoble, France. 2011
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Soumis le : jeudi 24 février 2011 - 11:21:39
Dernière modification le : jeudi 11 janvier 2018 - 01:49:32
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  • HAL Id : inria-00569077, version 1



Majdi Elhaji, Pierre Boulet, Rached Tourki, Abdelkrim Zitouni, Jean-Luc Dekeyser, et al.. Modeling Networks-on-Chip at System Level with the MARTE UML profile. M-BED'2011, Mar 2011, Grenoble, France. 2011. 〈inria-00569077〉



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