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Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach

Abstract : Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case performance are hard to be modeled for the WCET analysis. In this paper we present Patmos, a processor optimized for low WCET bounds rather than high average case performance. Patmos is a dual- issue, statically scheduled RISC processor. The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average case performance.
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Contributor : Florian Brandner Connect in order to contact the contributor
Submitted on : Tuesday, April 12, 2011 - 3:19:01 PM
Last modification on : Friday, November 18, 2022 - 9:24:51 AM
Long-term archiving on: : Thursday, November 8, 2012 - 4:11:41 PM


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Martin Schoeberl, Pascal Schleuniger, Wolfgang Puffitsch, Florian Brandner, Christian W. Probst, et al.. Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach. Bringing Theory to Practice: Predictability and Performance in Embedded Systems, Philipp Lucas, Lothar Thiele, Benoit Triquet, Theo Ungerer, and Reinhard Wilhelm, Mar 2011, Grenoble, France. pp.11-21, ⟨10.4230/OASIcs.PPES.2011.11⟩. ⟨inria-00585320⟩



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