M. Duranton, S. Yehia, B. D. Sutter, K. De-bosschere, A. Cohen et al., The HiPEAC Vision, Network of Excellence of High Performance and Embedded Architecture and Compilation, 2010.
URL : https://hal.archives-ouvertes.fr/hal-01491758

C. Bertin, C. Guillon, and K. De-bosschere, Compilation and virtualization in the HiPEAC vision, Proceedings of the 47th Design Automation Conference on, DAC '10, 2010.
DOI : 10.1145/1837274.1837302

R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing et al., The worst-case execution-time problem???overview of methods and survey of tools, ACM Transactions on Embedded Computing Systems, vol.7, issue.3, pp.1-53, 2008.
DOI : 10.1145/1347375.1347389

C. Pitter and M. Schoeberl, A real-time Java chip-multiprocessor ARM Jazelle technology, TECS, vol.10, issue.1, 2010.

A. Cohen and E. Rohou, Processor virtualization and split compilation for heterogeneous multicore embedded systems, Proceedings of the 47th Design Automation Conference on, DAC '10, 2010.
DOI : 10.1145/1837274.1837303

URL : https://hal.archives-ouvertes.fr/inria-00472274

G. Bernat, A. Burns, and A. J. Wellings, Portable worst-case execution time analysis using Java Byte Code, Proceedings 12th Euromicro Conference on Real-Time Systems. Euromicro RTS 2000, pp.81-88, 2000.
DOI : 10.1109/EMRTS.2000.853995

I. Bate, G. Bernat, G. Murphy, and P. P. Puschner, Low-level analysis of a portable Java byte code WCET analysis framework, Proceedings Seventh International Conference on Real-Time Computing Systems and Applications, pp.39-46, 2000.
DOI : 10.1109/RTCSA.2000.896369

H. Theiling, C. Ferdinand, and R. Wilhelm, Fast and precise WCET prediction by separated cache and path analyses, Real-Time Systems, vol.18, issue.2/3, pp.157-179, 2000.
DOI : 10.1023/A:1008141130870

F. Mueller, Timing analysis for instruction caches, Real-Time Systems, vol.18, issue.2/3, pp.217-247, 2000.
DOI : 10.1023/A:1008145215849

R. Heckmann, M. Langenbach, S. Thesing, and R. Wilhelm, The influence of processor architecture on the design and the results of WCET tools, Proceedings of the IEEE, vol.91, issue.7, pp.1038-1054, 2003.
DOI : 10.1109/JPROC.2003.814618

D. Hardy and I. Puaut, WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches, 2008 Real-Time Systems Symposium, pp.456-466, 2008.
DOI : 10.1109/RTSS.2008.10

M. Garatti, FICO: A Fast Instruction Cache Optimizer, SCOPES, pp.388-402, 2003.
DOI : 10.1007/978-3-540-39920-9_27

P. Lokuciejewski, H. Falk, and P. Marwedel, WCET-driven Cache-based Procedure Positioning Optimizations, 2008 Euromicro Conference on Real-Time Systems, pp.321-330, 2008.
DOI : 10.1109/ECRTS.2008.20

T. Harmon, M. Schoeberl, R. Kirner, and R. Klefstad, A modular worstcase execution time analysis tool for Java processors, RTAS, pp.47-57, 2008.

R. Kirner and M. Schoeberl, Modeling the function cache for worstcase execution time analysis, DAC, pp.471-476, 2007.

M. Schoeberl, W. Puffitsch, R. U. Pedersen, and B. Huber, Worst-case execution time analysis for a Java processor, Software: Practice and Experience, pp.507-542, 2010.
DOI : 10.1002/spe.968

J. S. Auerbach, D. F. Bacon, B. Blainey, P. Cheng, M. Dawson et al., Design and implementation of a comprehensive real-time java virtual machine, Proceedings of the 7th ACM & IEEE international conference on Embedded software , EMSOFT '07, pp.249-258, 2007.
DOI : 10.1145/1289927.1289967

T. Kotzmann, C. Wimmer, H. Mössenböck, T. Rodriguez, K. Russell et al., Design of the Java HotSpot TM client compiler for Java 6, pp.1-7, 2008.

P. Cousot and R. Cousot, Abstract interpretation, Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages , POPL '77, pp.238-252, 1977.
DOI : 10.1145/512950.512973

URL : https://hal.archives-ouvertes.fr/inria-00528590

J. Reineke, D. Grund, C. Berg, and R. Wilhelm, Timing predictability of cache replacement policies, Real-Time Systems, vol.28, issue.2???3, pp.99-122, 2007.
DOI : 10.1007/s11241-007-9032-3

]. N. Holsti, T. Långbacka, and S. Saarinen, Using a worst-case execution time tool for real-time verification of the DEBIE software, Data Systems in Aerospace (DASIA), 2000.

P. Puschner and A. V. Schedl, Computing maximum task execution times ? a graph based approach, RTSS Constraint Integer Programming, pp.67-91, 1153.

O. Traub, G. Holloway, and M. D. Smith, Quality and speed in linearscan register allocation, PLDI. ACM, pp.142-151, 1998.

C. Lee, M. Potkonjak, and W. H. Mangione-smith, MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems, MICRO, pp.330-335, 1997.