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Polychronous Controller Synthesis from MARTE CCSL Timing Specifications

Abstract : The UML Profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) defines a mathematically expressive model of time, the Clock Constraint Specification Language (CCSL), to specify timed annotations on UML diagrams and thus provides them with formally defined timed interpretations. Thanks to its expressive capability, the CCSL allows for the specification of static and dynamic properties, of deterministic and non-deterministic behaviors, or of systems with multiple clock domains. Code generation from such multiclocked specifications (for the purpose of synthesizing a simulator, for instance) is known to be a difficult issue. We address it by using the approach of controller synthesis. In our framework, a timed CCSL specification is regarded as a property whose satisfaction should be enforced for any UML diagram carrying it as annotation. To do so, CCSL statements are first translated into dynamical polynomial systems. Such systems can be manipulated using the model-checker Sigali to synthesize an executable property (a controller) which enforces the satisfaction of the specified timing constraints on the UML diagram with which it is executed.
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https://hal.inria.fr/inria-00594942
Contributor : Yu Huafeng <>
Submitted on : Sunday, May 22, 2011 - 12:31:51 PM
Last modification on : Friday, January 8, 2021 - 3:40:41 AM
Long-term archiving on: : Tuesday, August 23, 2011 - 2:20:59 AM

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  • HAL Id : inria-00594942, version 1

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Huafeng Yu, Jean-Pierre Talpin, Loïc Besnard, Thierry Gautier, Hervé Marchand, et al.. Polychronous Controller Synthesis from MARTE CCSL Timing Specifications. ACM/IEEE Ninth International Conference on Formal Methods and Models for Codesign (MEMOCODE), Jul 2011, Cambridge, United Kingdom. ⟨inria-00594942⟩

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