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Deadlock free control synthesis for partially controllable marked graphs

Abstract : This paper deals with the problem of deadlock avoidance in control synthesis for a discrete event systems modeled by marked graphs. The specifications are modeled by General Mutual Exclusion Constraints. We show that, even that the system to be controlled is live, the restriction introduced by the controller may generate deadlocks. Therefore, the research work we present in this paper focuses on enhancing an existing control synthesis technique in order to provide a deadlock free maximal permissive control law.
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https://hal.inria.fr/inria-00600962
Contributor : Ist Inria Nancy Grand Est <>
Submitted on : Thursday, June 16, 2011 - 12:09:53 PM
Last modification on : Sunday, November 22, 2020 - 12:18:02 PM

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Hatem Sioud, Alexandre Sava, Z. Achour, Nidhal Rezg. Deadlock free control synthesis for partially controllable marked graphs. 12th IFAC Symposium on Large Scale Systems: Theory and Applications - LSS 2010, 2010, Lille, France. ⟨10.3182/20100712-3-FR-2020.00030⟩. ⟨inria-00600962⟩

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