S. Andalam, P. Roop, and A. Girault, Predictable multithreading of embedded applications using PRET-C, Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010.
DOI : 10.1109/MEMCOD.2010.5558636

URL : https://hal.archives-ouvertes.fr/hal-00786378

A. Benveniste, P. Caspi, S. Edwards, N. Halbwachs, P. L. Guernic et al., The synchronous languages 12 years later, Proceedings of the IEEE, pp.64-83, 2003.
DOI : 10.1109/JPROC.2002.805826

G. Berry and G. Gonthier, The Esterel synchronous programming language: design, semantics, implementation, Science of Computer Programming, vol.19, issue.2, pp.87-152, 1992.
DOI : 10.1016/0167-6423(92)90005-V

URL : https://hal.archives-ouvertes.fr/inria-00075711

V. Bertin, Taxys = Esterel + Kronos -a tool for verifying realtime properties of embedded systems, IEEE Conference on Decision and Control, 2001.

M. Boldt, C. Traulsen, and R. Von-hanxleden, Worst Case Reaction Time Analysis of Concurrent Reactive Programs, Electronic Notes in Theoretical Computer Science, vol.203, issue.4, pp.65-79, 2008.
DOI : 10.1016/j.entcs.2008.05.011

F. Boussinot, Reactive C: An extension of C to program reactive systems. Software Practice and Experience, pp.401-428, 1991.

S. A. Edwards and J. Zeng, Code generation in the Columbia Esterel Compiler, EURASIP Journal on Embedded Systems, 2007.

B. Huber and M. Schoeberl, Comparison of implicit path enumeration and model checking based WCET Analysis, Proceedings of the 9th International Workshop on Worst-Case Execution Time (WCET) Analysis, pp.23-34, 2009.

L. Ju, B. K. Huynh, S. Chakraborty, and A. Roychoudhury, Contextsensitive timing analysis of Esterel programs, DAC '09: Proceedings of the 46th Annual Design Automation Conference, pp.870-873, 2009.

L. Ju, B. K. Huynh, A. Roychoudhury, and S. Chakraborty, Performance debugging of Esterel specifications, Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, CODES/ISSS '08, pp.173-178, 2008.
DOI : 10.1145/1450135.1450175

L. Ju, B. K. Huynh, A. Roychoudhury, and S. Chakraborty, Timing analysis of esterel programs on general-purpose multiprocessors, Proceedings of the 47th Design Automation Conference on, DAC '10, pp.48-51, 2010.
DOI : 10.1145/1837274.1837288

F. Laroussinie, N. Markey, and P. Schnoebelen, Model Checking Timed Automata with One or Two Clocks, In CONCUR, vol.1, issue.4, pp.387-401, 2004.
DOI : 10.1007/3-540-45931-6_19

URL : https://hal.archives-ouvertes.fr/hal-01194617

G. Logothetis, K. Schneider, and C. Metzler, Generating formal models for real-time verification by exact low-level runtime analysis of synchronous programs, Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748), pp.256-264, 2003.
DOI : 10.1109/REAL.2003.1253272

M. Mendler, R. Von-hanxleden, and C. Traulsen, WCRT algebra and interfaces for esterel-style synchronous processing, 2009 Design, Automation & Test in Europe Conference & Exhibition, 2009.
DOI : 10.1109/DATE.2009.5090639

A. Metzner, Why Model Checking Can Improve WCET Analysis, CAV, pp.334-347, 2004.
DOI : 10.1007/978-3-540-27813-9_26

P. S. Roop, S. Andalam, R. Von-hanxleden, S. Yuan, and C. Traulsen, Tight WCRT analysis of synchronous C programs, Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems, CASES '09, 2009.
DOI : 10.1145/1629395.1629424

V. Suhendra, T. Mitra, A. Roychoudhury, and T. Chen, Efficient detection and exploitation of infeasible paths for software timing analysis, Proceedings of the 43rd annual conference on Design automation , DAC '06, pp.358-363, 2006.
DOI : 10.1145/1146909.1147002

R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing et al., The worst-case execution-time problem???overview of methods and survey of tools, ACM Transactions on Embedded Computing Systems, vol.7, issue.3, pp.1-53, 2008.
DOI : 10.1145/1347375.1347389