FPGA-Specific Synthesis of Loop-Nests with Pipelined Computational Cores

Christophe Alias 1, * Bogdan Pasca 2 Alexandru Plesco 1
* Corresponding author
1 COMPSYS - Compilation and embedded computing systems
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
2 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : Increases in the capacities and features of FPGAs has opened a new perspective on their use as application accelerators. However, in order for FPGAs to be accepted is mainstream solutions, the long design cycles must be shortened by using high-level synthesis tools in the design process. Current HLS tools targeting FPGAs come with several limitations, and one of them is the efficient use of pipelined arithmetic operators, commonly encountered in high-throughput FPGA designs. We focus here on the efficient generation of FPGA-specific hardware accelerators for regular codes with perfect loop nests where inner statements are implemented as a pipelined arithmetic operator, which is often the case of scientific codes using floating-point arithmetic. We propose a semi-automatic code generation process where the arithmetic operator is identified and generated. Its pipeline information is used to reschedule the initial program execution in order to keep the operator's pipeline as ''busy'' as possible, while minimizing memory access. Next, we show how our method can be used as a tool to generate control FSMs of multiple parallel computing cores. Finally, we show that accounting for the application's accuracy needs allows designing smaller and faster operators.
Complete list of metadatas

Cited literature [30 references]  Display  Hide  Download

https://hal.inria.fr/inria-00606977
Contributor : Christophe Alias <>
Submitted on : Saturday, January 7, 2012 - 7:00:07 AM
Last modification on : Thursday, February 7, 2019 - 4:14:30 PM
Long-term archiving on : Tuesday, December 13, 2016 - 6:36:57 PM

File

RR-7674.pdf
Files produced by the author(s)

Identifiers

  • HAL Id : inria-00606977, version 1

Collections

Citation

Christophe Alias, Bogdan Pasca, Alexandru Plesco. FPGA-Specific Synthesis of Loop-Nests with Pipelined Computational Cores. [Research Report] RR-7674, INRIA. 2011, pp.33. ⟨inria-00606977⟩

Share

Metrics

Record views

327

Files downloads

412