High Level Design of adaptive distributed controller for Partial Dynamic reconfiguration in FPGA

Sana Cherif 1, 2, * Chiraz Trabelsi 1, 2 Samy Meftali 1, 2 Jean-Luc Dekeyser 1, 2
* Auteur correspondant
1 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, Inria Lille - Nord Europe
Abstract : Controlling dynamic and partial reconfigurations becomes one of the most important key issues in modern embedded systems design. In fact, in such systems, the reconfiguration controller can significantly affect the system performances. Indeed, the controller has to handle efficiently three major tasks during runtime: observation (monitoring), taking reconfiguration decisions and notify decisions to the rest of the system in order to realize it. We present in this paper a novel high level approach permitting to model, using MARTE UML profile, modular and flexible distributed controllers for dynamic reconfiguration management. This approach permits components/ models reuse and allows systematic code generation. It consequently makes reconfigurable systems design less tedious and reduces time to market.
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Communication dans un congrès
Proceeding of Design and Architectures for Signal and Image Processing, DASIP 2011, Nov 2011, Tampere, Finland. 2011
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Sana Cherif, Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser. High Level Design of adaptive distributed controller for Partial Dynamic reconfiguration in FPGA. Proceeding of Design and Architectures for Signal and Image Processing, DASIP 2011, Nov 2011, Tampere, Finland. 2011. 〈inria-00609122〉

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