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Layout Guidelines for 3D Architectures including Optical Ring Network-on-Chip (ORNoC)

Abstract : Trends in design of the next generation of Multi-Processors System on Chip (MPSoC) point to 3D integration of thousand of processing elements, requiring high performance interconnect for high throughput and low latency communications. Optical on-chip interconnects enable significantly increased bandwidth and decreased latency. They are thus considered as one of the most promising paradigms for the design of such system. However, existence of interfaces between electronic and photonic signals implies strong constraints on the layout of the 3D architecture and may impact the architecture scalability. In this paper, we propose and evaluate a possible layout for an optical Network-on-Chip used to interconnect processing elements located on different electrical layers.
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Contributor : Sébastien Le Beux Connect in order to contact the contributor
Submitted on : Friday, September 2, 2011 - 11:50:34 AM
Last modification on : Thursday, August 4, 2022 - 5:15:29 PM
Long-term archiving on: : Tuesday, November 13, 2012 - 9:45:56 AM


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  • HAL Id : inria-00618605, version 1



Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu. Layout Guidelines for 3D Architectures including Optical Ring Network-on-Chip (ORNoC). 19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2011, Hong Kong, China. ⟨inria-00618605⟩



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