M. Alonso, S. Coll, J. Martínez, V. Santonja, P. et al., Dynamic power saving in fat-tree interconnection networks using on/off links, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium, 2006.
DOI : 10.1109/IPDPS.2006.1639599

G. Blake, R. Dreslinski, and T. Mudge, A survey of multicore processors, IEEE Signal Processing Magazine, vol.26, issue.6, pp.26-37, 2009.
DOI : 10.1109/MSP.2009.934110

J. Duato, A new theory of deadlock-free adaptive routing in wormhole networks, IEEE Trans. Parallel Distrib. Syst, pp.1320-1331, 1993.

L. Gravano, G. D. Pifarré, P. E. Berman, and J. L. Sanz, Adaptive deadlock- and livelock-free routing with all minimal paths in torus networks, IEEE Transactions on Parallel and Distributed Systems, vol.5, issue.12, pp.1233-1251, 1994.
DOI : 10.1109/71.334898

K. Gunther, Prevention of Deadlocks in Packet-Switched Data Transport Systems, IEEE Transactions on Communications, vol.29, issue.4, pp.512-524, 1981.
DOI : 10.1109/TCOM.1981.1095021

Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar, A 5-GHz Mesh Interconnect for a Teraflops Processor, IEEE Micro, vol.27, issue.5, pp.51-61, 2007.
DOI : 10.1109/MM.2007.4378783

J. Kim and M. A. Horowitz, Adaptive supply serial links with sub-1V operation and per-pin clock recovery, Proceedings of Int. Solid-State Circuits Conf, pp.1403-1413, 2002.

M. A. Kinsy, M. H. Cho, T. Wen, E. Suh, M. Van-dijk et al., Application-aware deadlock-free oblivious routing, Proceedings of the 36th annual Int. Symp. on Computer architecture, pp.208-219, 2009.
DOI : 10.1145/1555815.1555782
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.153.4632

C. Lee and N. Jha, FinFET-based dynamic power management of onchip interconnection networks through adaptive back-gate biasing, Proceedings of ICCD 2009, the IEEE Int. Conf. on Computer Design, pp.350-357, 2009.

S. E. Lee and N. Bagherzadeh, A variable frequency link for a power-aware network-on-chip (NoC), Integration, the VLSI Journal, vol.42, issue.4, pp.479-485, 2009.
DOI : 10.1016/j.vlsi.2009.01.002

F. Li, G. Chen, and M. T. Kandemir, Compiler-directed voltage scaling on communication links for reducing power consumption, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005., pp.456-460, 2005.
DOI : 10.1109/ICCAD.2005.1560111

J. Li, W. Huang, C. Lefurgy, L. Zhang, W. E. Denzel et al., Power shifting in Thrifty Interconnection Network, 2011 IEEE 17th International Symposium on High Performance Computer Architecture, pp.156-167, 2011.
DOI : 10.1109/HPCA.2011.5749725

N. Michael, M. Nikolov, A. Tang, G. E. Suh, and C. Batten, Analysis of application-aware on-chip routing under traffic uncertainty, Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, NOCS '11, pp.9-16, 2011.
DOI : 10.1145/1999946.1999949

J. D. Owens, W. J. Dally, R. Ho, D. N. Jayasimha, S. W. Keckler et al., Research Challenges for On-Chip Interconnection Networks, IEEE Micro, vol.27, issue.5, pp.96-108, 2007.
DOI : 10.1109/MM.2007.4378787

P. Renaud-goud, Source code for the simulations

D. Seo, A. Ali, W. Lim, and N. Rafique, Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks, Proceedings of ISCA'05, the 32nd Int. Symp. on Computer Architecture, pp.432-443, 2005.
DOI : 10.1145/1080695.1070006

L. Shang, L. Peh, and N. Jha, Dynamic voltage scaling with links for power optimization of interconnection networks, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings., pp.91-102, 2003.
DOI : 10.1109/HPCA.2003.1183527

D. Shin, Power-aware communication optimization for networks-on-chips with voltage scalable links, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis , CODES+ISSS '04, pp.170-175, 2004.
DOI : 10.1145/1016720.1016763