Stream and Memory Hierarchy Design for Multi-Purpose Accelerators

Sylvain Girbal 1 Sami Yehia 1 Hugues Berry 2 Olivier Temam 3
2 COMBINING - COMputational BIology and data miNING
LIRIS - Laboratoire d'InfoRmatique en Image et Systèmes d'information, Inria Grenoble - Rhône-Alpes
3 ALCHEMY - Architectures, Languages and Compilers to Harness the End of Moore Years
LRI - Laboratoire de Recherche en Informatique, UP11 - Université Paris-Sud - Paris 11, Inria Saclay - Ile de France, CNRS - Centre National de la Recherche Scientifique : UMR8623
Abstract : Power and programming challenges make heterogeneous multi-cores composed of cores and ASICs an attractive alternative to homogeneous multi-cores. Recently, multi-purpose loop-based generated accelerators have emerged as an especially attractive accelerator option. They have several assets: short design time (automatic generation), flexibility (multi-purpose) but low configuration and routing overhead (unlike FPGAs), computational performance (operations are directly mapped to hardware), and a focus on memory throughput by leveraging loop constructs. However, with multiple streams, the memory behavior of such accelerators can become at least as complex as that of superscalar processors, while they still need to retain the memory ordering predictability and throughput efficiency of DMAs. In this article, we show how to design a memory interface for multi-purpose accelerators which combines the ordering predictability of DMAs, retains key efficiency features of memory systems for complex processors, and requires only a fraction of their cost by leveraging the properties of streams references. We evaluate the approach with a synthesizable version of the memory interface for an example 9-task generated loopbased accelerator
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Communication dans un congrès
1st Workshop on SoC Architecture, Accelerators and Workloads (SAW-1), Jan 2010, Bangalore, India. 2010
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Sylvain Girbal, Sami Yehia, Hugues Berry, Olivier Temam. Stream and Memory Hierarchy Design for Multi-Purpose Accelerators. 1st Workshop on SoC Architecture, Accelerators and Workloads (SAW-1), Jan 2010, Bangalore, India. 2010. 〈inria-00633580〉

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