, 3] Designing high-performance dsp hardware using Catapult C synthesis and the altera accelerated libraries. Mentor Graphics Technical Library, 2007.
, UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development, IEEE Computer Architecture Letters, vol.6, issue.2, pp.45-48, 2007.
DOI : 10.1109/L-CA.2007.12
, Sorting networks and their applications, AFIPS Spring Joint Computing Conference, pp.307-314, 1968.
, A simple binary random number generator: new approaches for CMOS VLSI, [1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems, pp.127-129, 1992.
DOI : 10.1109/MWSCAS.1992.271316
, Over-provisioned multicore processor, 2009.
, Programmable accelerator engines through retargetable customization, Proc. of Hot Chips 16, 2004.
, VEAL, ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture, pp.389-400, 2008.
DOI : 10.1145/1394608.1382155
, Bridging the computation gap between programmable processors and hardwired accelerators, 2009 IEEE 15th International Symposium on High Performance Computer Architecture, pp.313-322, 2009.
DOI : 10.1109/HPCA.2009.4798266
, Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers, SIGARCH Comput. Archit. News, vol.18, issue.3a, pp.364-373, 1990.
, A quantitative analysis of loop nest locality, ACM SIGPLAN Notices, vol.31, issue.9, pp.94-104, 1996.
DOI : 10.1145/248209.237161
, Reconciling specialization and flexibility through compound circuits, 2009 IEEE 15th International Symposium on High Performance Computer Architecture, pp.14-18, 2009.
DOI : 10.1109/HPCA.2009.4798263
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