Lattice-Based Memory Allocation, IEEE Transactions on Computers, pp.1242-1257, 2005. ,
URL : https://hal.archives-ouvertes.fr/hal-01272969
Code generation in the polyhedral model is easier than you think, Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004., pp.7-16, 2004. ,
DOI : 10.1109/PACT.2004.1342537
URL : https://hal.archives-ouvertes.fr/hal-00017260
On a graph-theoretical model for cyclic register allocation, Discrete Applied Mathematics, vol.93, issue.2-3, pp.191-203, 1999. ,
DOI : 10.1016/S0166-218X(99)00105-5
Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling, International Journal of Parallel Programming, vol.7, issue.3, pp.103-132, 1996. ,
DOI : 10.1007/BF03356744
Allocating Registers in Multiple Instruction-Issuing Processors, Proceedings of the IFIP WG 10.3 Working Conference on Parallel Architectures and Compilation Techniques , PACT'95, pp.290-293, 1995. ,
URL : https://hal.archives-ouvertes.fr/inria-00074059
OPTIMAL SOFTWARE PIPELINING UNDER RESOURCE CONSTRAINTS, International Journal of Foundations of Computer Science, vol.12, issue.06, pp.697-718, 2001. ,
DOI : 10.1142/S0129054101000825
SCAN: A Heuristic for Near-Optimal Software Pipelining, Euro-Par, 2006. ,
DOI : 10.1007/11823285_30
Minimum register instruction sequencing to reduce register spills in out-of-order issue superscalar architectures, IEEE Transactions on Computers, vol.52, issue.1, pp.4-20, 2003. ,
DOI : 10.1109/TC.2003.1159750
A register allocation framework based on hierarchical cyclic interval graphs, Lecture Notes in Computer Science, vol.641, p.176, 1992. ,
DOI : 10.1007/3-540-55984-1_17
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.31.6059
Register allocation for software pipelined multi-dimensional loops, ACM SIGPLAN Notices, vol.40, issue.6, pp.154-167, 2005. ,
DOI : 10.1145/1064978.1065030
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.83.4535
Compilers Strategies for Transport Triggered Architectures, 2001. ,
Software pipelining, PLDI, pp.318-328, 1988. ,
DOI : 10.1145/989393.989420
Register Allocation with Instruction Scheduling: A New Approach, SIGPLAN Notices, vol.28, issue.6, pp.248-257, 1993. ,
Scheduling of Tasks with Precedence Delays and Relative Deadlines -Framework for Time-optimal Dynamic Reconfiguration of FPGAs, IPDPS, pp.1-8, 2006. ,
Register Allocation and Optimal Spill Code Scheduling in Software Pipelined Loops Using 0-1 Integer Linear Programming Formulation, CC'07, pp.126-140, 2007. ,
Register Pressure in Instruction Level Paral- lelisme, 2002. ,
Register Saturation in Instruction Level Parallelism, International Journal of Parallel Programming, vol.21, issue.5, 2005. ,
DOI : 10.1007/s10766-005-6466-x
URL : https://hal.archives-ouvertes.fr/hal-00130633
On Periodic Register Need in Software Pipelining, IEEE Transactions on Computers, vol.56, issue.11, 2007. ,
DOI : 10.1109/TC.2007.70752
URL : https://hal.archives-ouvertes.fr/inria-00636095
Early Periodic Register Allocation on ILP Processors, Parallel Processing Letters, vol.14, issue.02, 2004. ,
DOI : 10.1142/S012962640400188X
URL : https://hal.archives-ouvertes.fr/hal-00130623
Schedule-independent storage mapping for loops, ACM SIGPLAN Notices, vol.33, issue.11, pp.24-33, 1998. ,
DOI : 10.1145/291006.291015
A unified framework for schedule and storage optimization, ACM SIGPLAN Notices, vol.36, issue.5, pp.232-242, 2001. ,
DOI : 10.1145/381694.378852
URL : https://hal.archives-ouvertes.fr/hal-00808285
Decomposed Software Pipelining with Reduced Register Requirement, Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT95, pp.277-280, 1995. ,