Optimal Software Pipelining with Functional Units and Registers, 1995. ,
On a graph-theoretical model for cyclic register allocation, Discrete Applied Mathematics, vol.93, issue.2-3, pp.191-203, 1999. ,
DOI : 10.1016/S0166-218X(99)00105-5
Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling, International Journal of Parallel Programming, vol.7, issue.3, pp.103-132, 1996. ,
DOI : 10.1007/BF03356744
Allocating Registers in Multiple Instruction-Issuing Processors, Proceedings of the IFIP WG 10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT'95, pp.290-293, 1995. ,
URL : https://hal.archives-ouvertes.fr/inria-00074059
OPTIMAL SOFTWARE PIPELINING UNDER RESOURCE CONSTRAINTS, International Journal of Foundations of Computer Science, vol.12, issue.06, pp.697-718, 2001. ,
DOI : 10.1142/S0129054101000825
Algorithmic Graph Theory and Perfect Graphs, 1980. ,
Algorithmique du décalage d'instructions, 2001. ,
A register allocation framework based on hierarchical cyclic interval graphs, Lecture Notes in Computer Science, vol.641, p.176, 1992. ,
DOI : 10.1007/3-540-55984-1_17
Lifetime-Sensitive Modulo Scheduling, PLDI 93, pp.258-267, 1993. ,
Compilers Strategies for Transport Triggered Architectures, 2001. ,
Retiming synchronous circuitry, Algorithmica, vol.9, issue.No. 1, pp.5-35, 1991. ,
DOI : 10.1007/BF01759032
Register requirements of pipelined processors, Proceedings of the 6th international conference on Supercomputing , ICS '92, pp.260-271, 1992. ,
DOI : 10.1145/143369.143419
Optimal loop scheduling with register constraints using flow graphs, 7th International Symposium on Parallel Architectures, Algorithms and Networks, 2004. Proceedings., pp.180-186, 2004. ,
DOI : 10.1109/ISPAN.2004.1300478
A novel framework of register allocation for software pipelining, Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages , POPL '93, pp.29-42, 1993. ,
DOI : 10.1145/158511.158519
Register allocation for software pipelined loops, Proceedings of the ACM SIGPLAN '92 Conference on Programming Language Design and Implementation, pp.283-299, 1992. ,
DOI : 10.1145/143103.143141
Pipeline Logiciel: Découplage et Contraintes de Registres, 1997. ,
Theory of Linear and Integer Programming, 1987. ,
Complete Register Allocation Problems, SIAM Journal on Computing, vol.4, issue.3, pp.226-248, 1975. ,
DOI : 10.1137/0204020
Register Saturation in Instruction Level Parallelism, International Journal of Parallel Programming, vol.21, issue.5, 2005. ,
DOI : 10.1007/s10766-005-6466-x
URL : https://hal.archives-ouvertes.fr/hal-00130633
Early Periodic Register Allocation on ILP Processors, Parallel Processing Letters, vol.14, issue.02, 2004. ,
DOI : 10.1142/S012962640400188X
URL : https://hal.archives-ouvertes.fr/hal-00130623
Coloring a Family of Circular Arcs, SIAM Journal on Applied Mathematics, vol.29, issue.3, pp.493-502, 1975. ,
DOI : 10.1137/0129040
Decomposed software pipelining: A new perspective and a new approach, International Journal of Parallel Programming, vol.19, issue.7, pp.351-373, 1994. ,
DOI : 10.1007/BF02577737
Software pipelining with register allocation and spilling, Proceedings of the 27th annual international symposium on Microarchitecture , MICRO 27, pp.95-99, 1994. ,
DOI : 10.1145/192724.192734