G. Chrysos and J. Emer, Memory Dependence Prediction using Store Sets, Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA- 98), pp.142-154, 1998.
DOI : 10.1109/isca.1998.694770

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.10.6285

W. Jalby, C. Lemuet, and S. Touati, An Efficient Memory Operations Optimization Technique for Vector Loops on Itanium 2 Processors. Conucurrency and Computation: Practice and Experience, 2004.

M. Johnson, Superscalar Microprocessor Design

S. Onder, Cost effective memory dependence prediction using speculation levels and color sets, Proceedings.International Conference on Parallel Architectures and Compilation Techniques, 2002.
DOI : 10.1109/PACT.2002.1106021

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.134.2308

I. Park, C. L. Ooi, and T. N. Vijaykumar, Reducing design complexity of the load/store queue, 22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449), 2003.
DOI : 10.1109/MICRO.2003.1253245

S. Sethumadhavan, R. Desikan, D. Burger, C. R. Moore, and S. W. Keckler, Scalable Hardware Memory Disambiguation for High ILP Processors, Proceedings of the 36th International Symposium on Microarchitecture (MICRO-36 2003), 2003.
DOI : 10.1109/micro.2003.1253244

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.140.6288

A. Yoaz, M. Erez, R. Ronen, and S. Jourdan, Speculation Techniques for Improving Load Related Instruction Scheduling, 26th Annual International Symposium on Computer Architecture (26th ISCA'99), Computer Architecture News, pp.42-53, 1999.
DOI : 10.1145/307338.300983

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.15.9659