D. Berson, R. Gupta, and M. Soffa, URSA: A Unified ReSource Allocator for Registers and Functional Units in VLIW Architectures, Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, pp.243-254, 1993.

D. De-werra, C. Eisenbeis, S. Lelait, and B. Marmol, On a graph-theoretical model for cyclic register allocation, Discrete Applied Mathematics, vol.93, issue.2-3, pp.191-203, 1999.
DOI : 10.1016/S0166-218X(99)00105-5

J. C. Dehnert, P. Y. Hsu, and J. P. Bratt, Overlapped Loop Support in the Cydra 5, Proceedings of Third International Conference on Architectural Support for Programming Languages and Operating Systems, pp.26-38, 1989.

A. E. Eichenberger, E. S. Davidson, and S. G. Abraham, Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling, International Journal of Parallel Programming, vol.7, issue.3, pp.103-132, 1996.
DOI : 10.1007/BF03356744

W. Fen-lin, S. K. Reinhardt, and D. Burger, Reducing DRAM Latencies with an Integrated Memory Hierarchy Design, Proceedings of the 7th International Symposium on High- Performance Computer Architecture, 2001.

D. Fimmel and J. Muller, OPTIMAL SOFTWARE PIPELINING UNDER RESOURCE CONSTRAINTS, International Journal of Foundations of Computer Science, vol.12, issue.06, pp.697-718, 2001.
DOI : 10.1142/S0129054101000825

L. J. Hendren, G. R. Gao, E. R. Altman, and C. Mukerji, A register allocation framework based on hierarchical cyclic interval graphs, Lecture Notes in Computer Science, vol.641, p.176, 1992.
DOI : 10.1007/3-540-55984-1_17

R. Huff, Lifetime-Sensitive Modulo Scheduling, PLDI 93, pp.258-267, 1993.
DOI : 10.1145/173262.155115
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.54.6852

J. Janssen, Compilers Strategies for Transport Triggered Architectures, 2001.

C. E. Leiserson and J. B. Saxe, Retiming synchronous circuitry, Algorithmica, vol.9, issue.No. 1, pp.5-35, 1991.
DOI : 10.1007/BF01759032
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.368.3222

J. Llosa, Reducing the Impact of Register Pressure on Software Pipelined Loops, 1996.

Q. Ning and G. R. Gao, A novel framework of register allocation for software pipelining, Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages , POPL '93, pp.29-42, 1993.
DOI : 10.1145/158511.158519

B. R. Rau, M. Lee, P. P. Tirumalai, and M. S. Schlansker, Register allocation for software pipelined loops, Proceedings of the ACM SIGPLAN '92 Conference on Programming Language Design and Implementation, pp.283-299, 1992.
DOI : 10.1145/143103.143141

F. Sanchez and J. Cortadella, RESIS: A new methodology for register optimization in software pipelining, Proceedings of Second International Euro-Par Conference, Euro- Par'96, 1996.
DOI : 10.1007/BFb0024783

A. Sawaya, Pipeline Logiciel: Découplage et Contraintes de Registres, 1997.

B. Schlansker, S. Rau, and . Mahlke, Achieving High Levels of instruction-Level Parallelism with Reduced Hardware Complexity, 1994.

M. M. Strout, L. Carter, J. Ferrante, and B. Simon, Schedule-independent storage mapping for loops, ACM SIGPLAN Notices, vol.33, issue.11, pp.24-33, 1998.
DOI : 10.1145/291006.291015
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.30.4279

W. Thies, F. Vivien, J. Sheldon, and S. Amarasinghe, A unified framework for schedule and storage optimization, ACM SIGPLAN Notices, vol.36, issue.5, pp.232-242, 2001.
DOI : 10.1145/381694.378852
URL : https://hal.archives-ouvertes.fr/hal-00808285

S. Touati, EquiMax: A New Formulation of Acyclic Scheduling Problem for ILP Processors, Interaction between Compilers and Computer Architectures, 2001.
URL : https://hal.archives-ouvertes.fr/hal-00646739

S. Touati, Optimal Acyclic Fine-Grain Schedule with Cache Effects for Embedded and Real Time Systems, Proceedings of 9th nternational Symposium on Hardware/Software Codesign, CODES, 2001.
DOI : 10.1109/hsc.2001.924668
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.7.6514

S. Touati, Register Pressure in Instruction Level Parallelisme, 2002.
DOI : 10.1007/s10766-005-6466-x
URL : https://hal.archives-ouvertes.fr/tel-00007405

J. Wang, A. Krall, and M. A. Ertl, Decomposed Software Pipelining with Reduced Register Requirement, Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT95, pp.277-280, 1995.