Optimal acyclic fine-grain scheduling with cache effects for embedded and real time systems

Sid Touati 1
1 A3 - Advanced analysis to code optimization
UP11 - Université Paris-Sud - Paris 11, Inria Saclay - Ile de France
Abstract : To sustain the increases in processor performance, embedded and real-time systems need to find the best total schedule time when compiling their application. The optimal acyclic scheduling problem is a classical challenge which has been formulated using integer programming in lot of works. In this paper, we give a new formulation of acyclic instruction scheduling problem under registers and resources constraints in multiple instructions issuing processors with cache effects. Given a direct acyclic graph G=(V,E), the complexity of our integer linear programming model is bounded by O(|V|2) variables and O(|E|+|V|2) constraints. This complexity is better than the complexity of the existing techniques which includes a worst total schedule time factor.
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Communication dans un congrès
Hardware/Software Codesign, CODES 2001, Apr 2001, Copenhague, Denmark. ACM, Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001, pp.159 -164, 2001, 〈10.1109/HSC.2001.924668〉
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https://hal.inria.fr/inria-00637269
Contributeur : Sid Touati <>
Soumis le : lundi 31 octobre 2011 - 15:49:31
Dernière modification le : jeudi 9 février 2017 - 16:00:14
Document(s) archivé(s) le : mercredi 1 février 2012 - 02:22:56

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Sid Touati. Optimal acyclic fine-grain scheduling with cache effects for embedded and real time systems. Hardware/Software Codesign, CODES 2001, Apr 2001, Copenhague, Denmark. ACM, Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001, pp.159 -164, 2001, 〈10.1109/HSC.2001.924668〉. 〈inria-00637269〉

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