M. Bachir, Loop Unrolling Minimisation for Periodic Register Allocation, 2010.

M. Bachir, D. Gregg, and S. Touati, Using the Meeting Graph Framework to Minimise Kernel Loop Unrolling for Scheduled Loops, Proceedings of the 22nd International Workshop on Languages and Compilers for Parallel Computing, 2009.
DOI : 10.1007/978-3-642-13374-9_19

URL : https://hal.archives-ouvertes.fr/hal-00643759

M. Bachir, S. Touati, and A. Cohen, Post-pass periodic register allocation to minimise loop unrolling degree, LCTES '08: Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems, pp.141-150, 2008.
DOI : 10.1145/1379023.1375677

URL : https://hal.archives-ouvertes.fr/inria-00637218

A. Sawaya and C. Eisenbeis, Optimal loop parallelization under register constraints, 1996.
URL : https://hal.archives-ouvertes.fr/inria-00073911

R. Cytron and J. Ferrante, What's in a name? -or-the value of renaming for parallelism detection and storage allocation, Proceedings of the 1987 International Conference on Parallel Processing (ICPP), pp.19-27, 1987.

D. De-werra, . Ch, S. Eisenbeis, B. Lelait, and . Marmol, On a graph-theoretical model for cyclic register allocation, Discrete Applied Mathematics, vol.93, issue.2-3, pp.191-203, 1999.
DOI : 10.1016/S0166-218X(99)00105-5

D. De-werra, C. Eisenbeis, S. Lelait, and E. Stohr, Circular-arc graph coloring: On chords and circuits in the meeting graph, European Journal of Operational Research, vol.136, issue.3, pp.483-500, 2002.
DOI : 10.1016/S0377-2217(01)00058-3

J. C. Dehnert, Y. Peter, J. P. Hsu, and . Bratt, Overlapped loop support in the cydra 5, ASPLOS-III: Proceedings of the third international conference on Architectural support for programming languages and operating systems, pp.26-38, 1989.

C. Eisenbeis, S. Lelait, and B. Marmol, The meeting graph: a new model for loop cyclic register allocation, PACT '95: Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, pp.264-267, 1995.

L. J. Hendren, G. R. Gao, E. R. Altman, and C. Mukerji, A register allocation framework based on hierarchical cyclic interval graphs, CC '92: Proceedings of the 4th International Conference on Compiler Construction, pp.176-191, 1992.
DOI : 10.1007/3-540-55984-1_17

R. A. Huff, Lifetime-sensitive modulo scheduling. SIG- PLAN Not, pp.258-267, 1993.
DOI : 10.1145/173262.155115

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

P. Faraboschi, J. A. Fisher, and C. Young, Embedded Computing: a VLIW Approach to Architecture, Compilers and Tools, 2005.

M. Lam, Software pipelining, ACM SIGPLAN Notices, vol.39, issue.4, pp.318-328, 1988.
DOI : 10.1145/989393.989420

A. Nicolau, R. Potasman, and H. Wang, Register allocation, renaming and their impact on fine-grain parallelism, Proceedings of the Fourth International Workshop on Languages and Compilers for Parallel Computing, pp.218-235, 1992.
DOI : 10.1007/BFb0038667

B. R. Rau, M. Lee, P. P. Tirumalai, and M. S. Schlansker, Register allocation for software pipelined loops, ACM SIGPLAN Notices, vol.27, issue.7, pp.283-299, 1992.
DOI : 10.1145/143103.143141

S. Touati and C. Eisenbeis, Early Periodic Register Allocation on ILP Processors, Parallel Processing Letters, vol.14, issue.02, pp.287-313, 2004.
DOI : 10.1142/S012962640400188X

URL : https://hal.archives-ouvertes.fr/hal-00130623