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Conception d’architectures d’entrelaceurs parallèles pour les décodeurs de Turbo-Codes et de LDPC

Abstract : We live in the era of high data rate wireless applications (smart-phones, net-books, digital television, mobile broadband devices…) in which advanced technologies are included such as OFDM, MIMO and advanced error correction techniques to reliably transfer data at high rates on wireless networks. Turbo and LDPC codes are two families of codes that are extensively used in current communication standards due to their excellent error correction capabilities. For high throughput performance, decoders are implemented on parallel architectures in which more than one processing elements decode the received data. However, parallel architectures suffer from memory conflict problem. It increases latency of memory accesses due to the presence of conflict management mechanisms in communication network and unfortunately decreases system throughput while augmenting system cost. To tackle memory conflict problem, three different types of approaches are used in literature. In first type of approaches, “architecture friendly” codes are constructed with good error correction capabilities in order to reduce hardware cost. However, these codes originate problem at the channel interleaver. In the second type of approaches, flexible and scalable interconnection network are introduced to handle memory conflicts at run time. However, flexible networks suffer from large silicon area and increased latency. The third type of approaches are design time memory mapping approaches in which the resultant architectures consist of ROM blocks used to store configuration bits. The use of ROM blocks may be sufficient to design parallel architecture that supports single codeword or single application. However, to design hardware architecture that supports complete standard or different applications, ROM based approaches result in huge hardware cost. To reduce hardware cost, optimizations are required to use as less ROMs as possible to support different applications. In this thesis, we aim to design optimized parallel architectures. For this purpose, we have proposed two different categories of approaches. In the first category, we have proposed two optimized design time off-chip approaches that aim to limit the cost of final decoder architecture targeting the customization of the network and the use of in-place memory architecture. In the second category, we have introduced a new method in which both runtime and design time approaches are merged to design flexible decoder architecture. For this purpose, we have embedded memory mapping algorithms on-chip in order to execute them at runtime to solve conflict problem. The on-chip implementation replaces the multiple ROM blocks with a single RAM block to support multiple block lengths and/or to support multiple applications. Different experiments are performed by executing memory mapping approaches on several embedded processors.
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https://hal.inria.fr/tel-01096713
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Submitted on : Thursday, December 18, 2014 - 9:31:51 AM
Last modification on : Wednesday, October 14, 2020 - 4:09:18 AM
Long-term archiving on: : Monday, March 23, 2015 - 4:31:11 PM

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  • HAL Id : tel-01096713, version 1

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Saeed Ur Reehman. Conception d’architectures d’entrelaceurs parallèles pour les décodeurs de Turbo-Codes et de LDPC. Architectures Matérielles [cs.AR]. Université de Bretagne Sud, 2014. Français. ⟨tel-01096713⟩

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