Primer: Reed-Solomon Error Correction Codes Area and throughput optimized asip for multi-standard turbo decoding, Rapid System Prototyping (RSP), 2011 22 nd IEEE International Symposium on, pp.79-84, 2011. ,
Towards Radix-4, Parallel Interleaver Design to Support High-Throughput Turbo Decoding for Re-Configurability " 33rd IEEE SARNOFF Symposium, 2010. ,
Optimal decoding of linear codes for minimizing symbol error rate (Corresp.), IEEE Transactions on Information Theory, vol.20, issue.2, pp.284-287, 1974. ,
DOI : 10.1109/TIT.1974.1055186
A soft-input softoutput maximum a posteriori (map) module to decode parallel and serial concatenated codes, TDA Progress Report, pp.42-127, 1996. ,
Mapping Interleaving Laws to Parallel Turbo and LDPC Decoder Architectures, IEEE Transactions on Information Theory, vol.50, issue.9, 2004. ,
DOI : 10.1109/TIT.2004.833353
Near Shannon limit errorcorrecting coding and decoding: Turbo-codes. 1, Communications, 1993. ,
Technical Program, Conference Record, vol.22, pp.1064-1070, 1993. ,
Mathematical Theory of connecting network and telephone trafic, 1965. ,
On self-routing in Benes and shuffle exchange networks, Proceedings of the International Conference on Parallel Processing, pp.196-200, 1988. ,
A Design Approach Dedicated to Network-Based and Conflict-Free Parallel InterleaversA Memory Mapping Approach for Network and Controller Optimization in Parallel Interleaver ArchitecturesA Conflict-Free Memory Mapping Approach To Design Parallel Hardware Interleaver Architectures With Optimized Network And Controller, Proceedings of the 22th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2012 Proceedings of the 23th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2013 Proceedings of IEEE Workshop on Signal Processing Systems (SiPS), p.page XX-YY page XX-YY, 2012. ,
A Combinatorial Problem, Koninklijke Nederlandse Akademie v. Wetenschappen, vol.49, pp.758-764, 1946. ,
Static address generation easing: a design methodology for parallel interleaver architectures, Acoustics Speech and Signal Processing 2010 IEEE International Conference on, pp.1594-1597, 2010. ,
A memory Mapping Approach for Parallel Interleaver design with multiples read and write accesses, Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), 2010. ,
Density evolution for two improved BP-Based decoding algorithms of LDPC codes, IEEE Communications Letters, vol.6, issue.5, 2002. ,
DOI : 10.1109/4234.1001666
Variable-size interleaver design for parallel turbo decoder architecture, IEEE Trans. Communication, vol.53, p.11, 2005. ,
Parallel VLSI architectures and parallel interleaving design for low-latency MAP turbo decoders ,
Interconnection Networks an Engineering Approach, pp.20-30, 2003. ,
Frame structure channel coding and modulation for the second generation digital terrestrial television broadcasting system (DVB-T2), 2008. ,
On multiple slice turbo codes Reduced complexity iterative decoding of low-density parity check codes based on belief propagation, 3rd International Symposium On Turbo Codes and Related Topics, pp.343-346673, 1999. ,
Parallel turbo coding interleavers: avoiding collisions in accesses to storage elements, Electronics Letters, vol.38, issue.5, pp.232-234, 2002. ,
DOI : 10.1049/el:20020148
Complementary series, IEEE Transactions on Information Theory, vol.7, issue.2, pp.82-87, 1961. ,
DOI : 10.1109/TIT.1961.1057620
DAVINCI Non-Binary LDPC codes: Performance and Complexity Assessment, proc of Future Network & Mobile, 2010. ,
The Bell System Technical Journal, Bell Syst. Tech. J, vol.XXVI, issue.2, pp.147-160, 1950. ,
Parallel Interleavers Through Optimized Memory Address Remapping, IEEE Trans. VLSI Systems, vol.18, issue.6, pp.978-987, 2010. ,
Iterative Error Correction Turbo, Low-Density Parity-Check and Repeat?Accumulate Codes, 2010. ,
Implementation Issues of Scalable LDPC-Decoders, Proceeding of 3rd International Symposium on Turbo Codes and Related Topics, pp.291-294, 2003. ,
Design of dividable interleaver for parallel decoding in turbo codes A new Benes network control algorithm, Electron. Lett. IEEE Trans. Comput, vol.38, issue.22 6, pp.1362-136436, 1987. ,
Parallel Permutations of Data: A Benes Network Control Algorithm for Frequently Used Permutations, IEEE Transactions on Computers, vol.27, issue.7, pp.637-647, 1978. ,
DOI : 10.1109/TC.1978.1675164
Error control Coding " Pearson Education Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access; Multiplexing and Channel Coding (Release 8), Electronics letters, 1996. ,
High-throughput LDPC decoders, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.11, issue.6, pp.976-996, 2003. ,
DOI : 10.1109/TVLSI.2003.817545
Butterfly and benesbased on-chip communication networks for multiprocessor turbo decoding, Design, Automation Test in Europe Conference Exhibition, pp.1-6, 2007. ,
Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder, Proceedings of the 45th annual conference on Design automation, DAC '08, 2008. ,
DOI : 10.1145/1391469.1391582
Spc05-3: On the parallelism of convolutional turbo decoding and interleaving interference, Global Telecommunications Conference, p.2006, 2006. ,
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding, DATE, 2006. ,
A Self-Routing Benes Network and Parallel Permutation Algorithms, IEEE Transactions on Computers, vol.30, issue.5, pp.332-340, 1981. ,
DOI : 10.1109/TC.1981.1675791
Parallel Algorithms to Set Up the Benes Permutation Network, IEEE Transactions on Computers, vol.31, issue.2, pp.148-154, 1982. ,
DOI : 10.1109/TC.1982.1675960
Network-on-Chip-Centric Approach to Interleaving in High Throughput Channel Decoders, 2005 IEEE International Symposium on Circuits and Systems, pp.1766-1769, 2005. ,
DOI : 10.1109/ISCAS.2005.1464950
Probabilistic Reasoning in Intelligent Systems: Networks of Plausible reference, 1988. ,
Interconnection framework for high-throughput, flexible LDPC decoders, Proceedings of the Design Automation & Test in Europe Conference, 2006. ,
DOI : 10.1109/DATE.2006.243815
A Memory Mapping Approach based on Network Customization to Design Conflict-Free Parallel Hardware Architectures, Proceedings of the 24th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2014, pp.page XX-YY, 2014. ,
Embedding Polynomial Time Memory Mapping and Routing Algorithms on-chip to Design Configurable Decoder Architecture, Proceedings of the 39th IEEE International Conference on Acoustics, Speech and Signal Processing, 2014. ,
On-Chip Implementation Of Memory Mapping Algorithm To Support Flexible Decoder Architecture, Proceedings of the 38th IEEE International Conference on Acoustics, Speech and Signal Processing, 2013. ,
A dedicated approach to explore design space for hardware architecture of turbo decoders, SiPS IEEE Workshop on Signal Processing Systems, vol.2012, issue.17, pp.2012-288, 2012. ,
Implementation of a UMTS turbodecoder on dynamically reconfigurable platform, DATE, 2004. ,
A methodology based on transportation problem modeling for designing parallel interleaver architectures, Acoustics, Speech and Signal Processing (ICASSP) IEEE International Conference on, pp.1613-1616, 2011. ,
An approach based on edge coloring of tripartite graph for designing parallel ldpc interleaver architecture, Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, pp.1720-1723, 2011. ,
Bipartite edge coloring approach for designing parallel hardware interleaver architecture, 2012. ,
A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm, IEEE Transactions on Signal Processing, vol.61, issue.16, pp.16-4127, 2013. ,
DOI : 10.1109/TSP.2013.2264057
URL : https://hal.archives-ouvertes.fr/hal-00820779
A Theorem on Coloring the Lines of a Network, Proceedings of the IEEE Workshop on Signal Processing Systems The Mathematical Coloring Book Journal of Solid state circuits, pp.148-151, 1949. ,
DOI : 10.1002/sapm1949281148
On maximum contention-free interleavers and permutation polynomials over integer rings, IEEE Transactions on Information Theory, vol.52, issue.3, pp.1249-1253, 2006. ,
DOI : 10.1109/TIT.2005.864450
On an estimate of the chromatic class of a p-graph(In Russian), Diskret.Analiz, vol.3, pp.25-30, 1964. ,
High-throughput contention-free concurrent interleaver architecture for multi-standard turbo decoder Application-Specific Systems, Architectures and Processors (ASAP) Enabling high-speed turbo decoding through concurrent interleaving, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp.897-900, 2002. ,
Optimized Concurrent Interleaving for High-speed Turbo-Decoding, Proc. 9rh IEEE International Conference on Electronics, Circuits and Systems -ICECS 2002, 2002. ,
Concurrent interleaving architectures for high-throughput channel coding, 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03)., pp.613-616, 2003. ,
DOI : 10.1109/ICASSP.2003.1202441
02, Part 11 Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Enhancements for Higher Throughput, 2008. ,
16e, Part 16 Air Interface for Fixed and Mobile Broadband Wireless Access Systems Amendment 2: Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands, 2006. ,
SOC-Network for Interleaving in wireless Communications, MPSOC, 2004. ,
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture, IEEE Journal of Solid-State Circuits, vol.45, issue.2, pp.422-432, 2010. ,
DOI : 10.1109/JSSC.2009.2038428
High-efficiency processing schedule for parallel turbo decoders using qpp interleaver, IEEE Transations on Circuits and Systems, vol.58, pp.1412-1420, 2011. ,
Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System, IEEE Trans. Circuits Syst ,
Comparative study of turbo decoding techniques: an overview, IEEE Transactions on Vehicular Technology, vol.49, issue.6, pp.2208-2233, 2000. ,
DOI : 10.1109/25.901892
Regular and irregular progressive edge-growth Tanner graphs, IEEE Trans. Inf. Theory, pp.51-386, 2005. ,
Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder, Integration, the VLSI Journal, vol.44, issue.4, pp.305-315, 2011. ,
DOI : 10.1016/j.vlsi.2010.07.001
A parallel MAP algorithm for low latency turbo decoding, IEEE Communications Letters, vol.6, issue.7, pp.288-290, 2002. ,
DOI : 10.1109/LCOMM.2002.801310
Parallel turbo decoding, Proceedings of the ISCAS '04, pp.23-26, 2004. ,
Shuffled Iterative Decoding, IEEE Transactions on Communications, vol.53, issue.2, pp.209-213, 2005. ,
DOI : 10.1109/TCOMM.2004.841982
Iterative Decoding With Replicas, Proceedings of the 24th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2014, pp.1644-1663, 2007. ,
DOI : 10.1109/TIT.2007.894683
Embedding Polynomial Time Memory Mapping and Routing Algorithms on-chip to Design Configurable Decoder Architecture, Proceedings of the 39th IEEE International Conference on Acoustics, Speech and Signal Processing, 2014. ,
On-Chip Implementation Of Memory Mapping Algorithm To Support Flexible Decoder Architecture, Proceedings of the 38th IEEE International Conference on Acoustics, Speech and Signal Processing, 2013. ,
A dedicated approach to explore design space for hardware architecture of turbo decoders, SiPS IEEE Workshop on Signal Processing Systems, vol.2012, issue.17, pp.2012-288, 2012. ,
Designing optimized parallel interleaver architecture through network customization, Colloque national du GDR SoC-SiP, 2014. ,