M. Parallel-reconfiguration, 102 4.4.1 Modes of Parallel Dynamic Reconfiguration

.. Experimental-results, 104 4.5.1 Application scenario, Reconfiguration time, p.110

T. Homade and P. , 111 4.6.1 The architecture of the HoMade processor, p.117

$. 99%<, $$ 9?, 99%<)"$ !%&'$ !%&'$ !%&'$

J. , A. A. El, A. R. Ben, and H. S. Mladenovic-n, New MIP model for Multiprocessor Scheduling Problem with Communication Delays, Journal of Optimisation Letters, pp.10-1007

J. Ben-atitallah-r, C. D. Senn-e, . Lanoe-m, . J. Blouin-d, G. A. Abdallah et al., An efficient Framework for Power-Aware Design of Heterogeneous MPSoC Abstract Clock-based Design of a JPEG Encoder A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC Architectures A model driven design framework for regular and massively parallel embedded applications, ACM Transactions in Embedded Computing Systems (TECS), pp.487-501, 2011.

J. C. Trabelsi, A. R. Ben, M. S. , and J. A. Dekeyser-j-l, Microprocessors and Microsystems Embedded Hardware Design A Model-Driven Approach for Hybrid Power Estimation in Embedded Systems Design, SoC Virtual Prototyping for Intensive Signal Processing Applications, pp.176-189, 2011.

J. Revues-en-cours-de-révision, . Ben-atitallah-r, . Viswanathan-v, . J. Dekeyser-j-l, . B. Ouni et al., A Reconfigurable Technology-Centric Design Process for Avionic Simulation and Test Multi- Level Energy/Power-Aware Design Methodology for MPSoC, Submitted to IEEE Transactions on Industrial Informatics Mathematical Programming Models for Scheduling in a CPU/FPGA Architecture with Heterogeneous Communication delays. Submitted to Journal of Intelligent Manufacturing (JIM), 2014.

C. , A. K. Ben, A. R. , H. S. Dekeyser-j-l, C. Generic et al., Early Poweraware Design Space Exploration for Embedded Systems : MPEG-2 Case Study Model-Driven design flow for distributed control in reconfigurable FPGA systems Conference on Design & Architectures for Signal & Image Processing Dynamic reconfiguration of modular I/O IP cores for avionic applications Redefining the role of FPGAs in the next generation avionic systems, Conférences internationales avec actes et comité de lecture (33) Pixel Distribution Architecture for Parallel Video Processing International Conference on ReConFigurable Computing and FPGAs International Symposium on System-on-Chip 2014 9th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'2014) 22nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays PETS : Power and energy estimation tool at system-level. 15th International Symposium on Quality Electronic Design (ISQED) N. Real-time simulator supporting Heterogeneous CPU/FPGA architecture. International Conference on Industrial Engineering and Systems Management (IEEE IESM 2013), p.2014, 2013.

C. , A. A. El, A. R. Ben, . Artiba-a-c10, . O. Souissi et al., Mathematical Programming Models for Scheduling in a CPU Optimization Of Matching and Scheduling On Heterogeneous CPU/FPGA Architectures. 7th IFAC Confe- Curriculum Vitae rence on Manufacturing Modelling, Management, and Control Hybrid and multicore optimized architectures for test and simulation systems, ZEAU P. Path Planning : A 2013 Survey. International Conference on Industrial Engineering and Systems Management (IEEE IESM 2013)FPGA Architecture with Communication Delay. International Conference on Industrial Engineering and Systems Management (IEEE IESM 2013), I4e2 The 6th International ICST Conference on Simulation Tools and Techniques, 2013.

S. E. Senn, C. D. Belleudy-c, F. A. Ben, and A. R. , Dynamic reconfiguration of modular I/O IP cores for avionic applications, International Conference on ReConFigurable Computing and FPGAs, 2012.

D. , C. O. Souissi, A. R. Ben, A. A. Elmaghraby-s-c16, . Rethinagiri-s-k et al., Optimization Of Run-time Mapping On Heterogeneous CPU/FPGA Architectures Optimization and SIMulation (MOSIM 2012) An Efficient Power Estimation Methodology for Complex RISC Processor based Embedded Platforms . 22nd Great Lakes Symposium on VLSI (GLSVLSI 2012) Dynamic Slack Reclamation Strategy for Multiprocessor Systems, 15th EUROMICRO Conference on Digital System Design 9th International Conference on Modeling The 16 IEEE Mediterranean Electrotechnical Conference, 2012.

C. Rethinagiri-s-k, A. R. Ben, N. S. Senn-e, . Dekeyser-j-l-c20, . Rethinagiri-s-k et al., Fast and Accurate Hybrid Power Estimation Methodology for Embedded Systems A System Level Power Consumption Estimation for MPSoC, Hardware Implementation : The Avionic Test System Case-Study. Architectural Support for Programming Languages and Operating Systems Conference on Design & Architectures for Signal & Image Processing, Tampere FL International Symposium on System-on-Chip 2011 Hybrid System Level Power Consumption Estimation for FPGA-Based MPSoC. International Conference on Computer Design (ICCD'11) A prototyping environment for high performance reconfigurable computing. 6th International Workshop on Reconfigurable and Communication-centric Systems-on-Chip, 2011.

C. G. Afonso, A. R. Ben, . Belanger-n, S. S. Rubio-m, . C. Dekeyser-j-l et al., Toward Generic and Adaptive Avionic Test Systems Dynamically Reconfigurable Architecture for a Driver Assistant System An Improved Automotive Multiple Target Tracking System Design, NASA/ESA Conference on Adaptive Hardware and Systems IEEE Symposium on Application Specific Processors (SASP 2011) 13th EUROMICRO Conference on Digital System Design DSD'2010, 2010.

C. , C. H. Ben, A. R. , N. S. Dekeyser-j-l, . Abid-m-c28 et al., A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC Using the UML Profile for MARTE to MPSOC Co-design. First International Conference on Embedded Systems & Critical Applications, Tunisia MPSoC Power Estimation Framework at Transaction Level Modeling Multilevel MPSoC simulation using an MDE approach An MPSoC performance estimation framework using transaction level modeling, 15th IEEE International Conference on Emerging Techonologies and Factory Automation 12th EUROMICRO Conference on Digital System Design The 19th IEEE International Conference on Microelectronics (ICM 2007) IEEE International SoC Conference The 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTC- SA'07), 2007.

C. Ben-atitallah-r, N. S. Greiner-a, and M. S. Dekeyser-j-l, Estimating energy consumption for an MPSoC architectural exploration, Multilevel MPSoC performance evaluation using MDE approach. In International Symposium on System Architecture of Computing Systems (ARCS'06), 2006.

A. W. Vienna, . M. Bouain, A. R. Ben, . Masmoudi-n, and J. Dekeyser, Rapid Simulation and Performance Evaluation : Methods and Tools (RAPIDO 2014) in conjuction with Hipeac conference 2014 Design Space Exploration on Heterogeneous SoC : The H.264 encoder case-study, Open- PEOPLE : Open Power and Energy Optimization PLatform and Estimator. 14th Sophia- Curriculum Vitae, 2013.

A. Microelectronics-forum, S. W. Afonso, A. R. Ben, . W. Dekeyser-j-l, . Rethinagiri-s-k et al., An Effective Approach for Power Consumption Modeling of Complex Processor An efficient scalable MPSoC architecture for dynamic task distribution, PROGram for Research on Embedded Systems & Software, STW.ICT An MDE Approach for Energy Consumption Estimation in MPSoC Design. 2nd Workshop on Rapid Simulation and Performance Evaluation : Methods and Toolsthèse Santhosh Kumar Rethinagiri), p.186, 2008.

A. Abdallah, A. Gamatié, R. B. Atitallah, and J. Dekeyser, Abstract Clock-Based Design of a JPEG Encoder, IEEE Embedded Systems Letters, vol.4, issue.2, pp.29-32, 2012.
DOI : 10.1109/LES.2012.2189195

URL : https://hal.archives-ouvertes.fr/hal-00758171

G. Afonso, Z. Baklouti, D. Duvivier, R. B. Atitallah, E. Billauer et al., Heterogeneous CPU/FPGA Reconfigurable Computing System for Avionic Test Application, 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum, 2013.
DOI : 10.1109/IPDPSW.2013.111

URL : https://hal.archives-ouvertes.fr/hal-00922004

G. Afonso, R. B. Atitallah, N. Bélanger, M. Rubio, and J. Dekeyser, An efficient design methodology for hybrid avionic test systems, 2010 IEEE 15th Conference on Emerging Technologies & Factory Automation (ETFA 2010), 2010.
DOI : 10.1109/ETFA.2010.5641195

G. Afonso, R. B. Atitallah, N. Bélanger, M. Rubio, S. Stilkerich et al., Toward generic and adaptive avionic test systems, 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2011.
DOI : 10.1109/AHS.2011.5963949

URL : https://hal.archives-ouvertes.fr/hal-00842398

G. Afonso, R. B. Atitallah, and J. Dekeyser, Software implementation vs. hardware implementation: The avionic test system case-study, Architectural Support for Programming Languages and Operating Systems, 2012.
URL : https://hal.archives-ouvertes.fr/hal-00665162

G. Afonso, R. Ben-atitallah, J. Dekeyser, N. Belanger, and M. Rubio, A prototyping environment for high performance reconfigurable computing, 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2011.
DOI : 10.1109/ReCoSoC.2011.5981497

URL : https://hal.archives-ouvertes.fr/hal-00842399

G. Afonso, N. Damiani, N. Belanger, R. B. Atitallah, and M. Rubio, Hybrid and multicore optimized architectures for test and simulation systems, Proceedings of the 6th International ICST Conference on Simulation Tools and Techniques, SimuTools '13, 2013.

G. Afonso, W. Godard, R. B. Atitallah, and J. Dekeyser, Système de simulation et de test, pp.27092-2014

A. Cadi, R. B. Atitallah, and A. Artiba, Mathematical Programming Models for Scheduling in a CPU/FPGA Architecture with Communication Delay, International Conference on Industrial Engineering and Systems Management -IESM'2013, 2013.
URL : https://hal.archives-ouvertes.fr/hal-00946255

A. Cadi, R. B. Atitallah, S. Hanafi, N. Mladenovic, and A. Artiba, New mip model for multiprocessor scheduling problem with communication delays. Optimisation Letters, pp.10-1007, 2014.
URL : https://hal.archives-ouvertes.fr/hal-01104613

A. Cadi, O. Souissi, R. B. Atitallah, and A. Artiba, Mathematical programming models for scheduling in a cpu/fpga architecture with heterogeneous communication delays, 2014.
URL : https://hal.archives-ouvertes.fr/hal-01247399

K. Ali, R. Ben-atitallah, J. Dekeyser, and S. Hanafi, A generic pixel distribution architecture for parallel video processing, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14), 2014.
DOI : 10.1109/ReConFig.2014.7032547

URL : https://hal.archives-ouvertes.fr/hal-01070541

Z. Baklouti, D. Duvivier, R. B. Atitallah, A. Artiba, and N. Belanger, Real-time simulator supporting heterogeneous cpu/fpga architecture, International Conference on Industrial Engineering and Systems Management -IESM'2013, 2013.
URL : https://hal.archives-ouvertes.fr/hal-00922009

R. B. Atitallah, S. Niar, and J. Dekeyser, MPSoC power estimation framework at transaction level modeling, 2007 Internatonal Conference on Microelectronics, 2007.
DOI : 10.1109/ICM.2007.4497703

R. B. Atitallah, É. Piel, S. Niar, P. Marquet, and J. Dekeyser, A fast mpsoc virtual prototyping for intensive signal processing applications. Microprocessors and Microsystems -Embedded Hardware Design, pp.176-189, 2012.

R. B. Atitallah, E. Senn, D. Chillet, M. Lanoe, and D. Blouin, An Efficient Framework for Power-Aware Design of Heterogeneous MPSoC, IEEE Transactions on Industrial Informatics, vol.9, issue.1, pp.487-501, 2013.
DOI : 10.1109/TII.2012.2198657

URL : https://hal.archives-ouvertes.fr/hal-00921900

R. B. Atitallah, V. Viswanathan, N. Belanger, and J. Dekeyser, A reconfigurable technology-centric design process for avionic simulation and test, 2014.

M. Bouain, V. Viswanathan, R. B. Atitallah, and J. Dekeyser, Communicationcentric design for fmc based i/o system, 9th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'2014), 2014.
URL : https://hal.archives-ouvertes.fr/hal-01104610

H. Chtioui, R. B. Atitallah, S. Niar, J. Dekeyser, and M. Abid, A dynamic hybrid cache coherency protocol for shared-memory mpsoc, 12th Euromicro Conference on Digital System Design, 2009.

H. Chtioui, S. Niar, R. B. Atitallah, M. Zahran, J. Dekeyser et al., A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC Architectures, International Journal of Computer Applications, vol.47, issue.3, pp.45-50, 2012.
DOI : 10.5120/7172-9801

A. Gamatié, S. L. Beux, É. Piel, R. B. Atitallah, A. Etien et al., A Model-Driven Design Framework for Massively Parallel Embedded Systems, ACM Transactions on Embedded Computing Systems, vol.10, issue.4, p.39, 2011.
DOI : 10.1145/2043662.2043663

N. Harb, S. Niar, M. Saghir, Y. Hillali, and R. B. Atitallah, Dynamically reconfigurable architecture for a driver assistant system, 2011 IEEE 9th Symposium on Application Specific Processors (SASP), 2011.
DOI : 10.1109/SASP.2011.5941079

T. Lange, N. Harb, H. Liu, S. Niar, and R. B. Atitallah, An Improved Automotive Multiple Target Tracking System Design, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, 2010.
DOI : 10.1109/DSD.2010.54

I. Mhedhbi, R. B. Atitallah, and A. Jemai, Dynamic slack reclamation strategy for multiprocessor systems, 2012 16th IEEE Mediterranean Electrotechnical Conference, 2012.
DOI : 10.1109/MELCON.2012.6196591

URL : https://hal.archives-ouvertes.fr/hal-00699824

B. Neji, Y. Aydi, R. B. Atitallah, S. Meftaly, M. Abid et al., Multistage Interconnection Network for MPSoC: Performances study and prototyping on FPGA, 2008 3rd International Design and Test Workshop, 2008.
DOI : 10.1109/IDT.2008.4802456

B. Ouni, I. Mhedbi, C. Trabelsi, R. B. Atitallah, and C. Belleudy, Multi-level energy/power-aware design methodology for MPSoC, Journal of Parallel and Distributed Computing, vol.100, 2014.
DOI : 10.1016/j.jpdc.2016.03.013

S. K. Rethinagiri, R. B. Atitallah, S. Niar, E. Senn, and J. Dekeyser, Fast and accurate hybrid power estimation methodology for embedded systems, Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP), 2011.
DOI : 10.1109/DASIP.2011.6136852

URL : https://hal.archives-ouvertes.fr/hal-00760353

S. K. Rethinagiri, R. Ben-atitallah, J. Dekeyser, E. Senn, and S. Niar, An efficient power estimation methodology for complex RISC processor-based platforms, Proceedings of the great lakes symposium on VLSI, GLSVLSI '12, 2012.
DOI : 10.1145/2206781.2206839

URL : https://hal.archives-ouvertes.fr/hal-00675469

S. K. Rethinagiri, R. B. Atitallah, S. Niar, E. Senn, and J. Dekeyser, Hybrid system level power consumption estimation for FPGA-based MPSoC, 2011 IEEE 29th International Conference on Computer Design (ICCD), pp.239-246, 2011.
DOI : 10.1109/ICCD.2011.6081403

URL : https://hal.archives-ouvertes.fr/hal-00842401

S. K. Rethinagiri, O. Palomar, O. S. Unsal, A. Cristal, R. B. Atitallah et al., PETS: Power and energy estimation tool at system-level, Fifteenth International Symposium on Quality Electronic Design, 2014.
DOI : 10.1109/ISQED.2014.6783373

M. Rubio, N. Belanger, R. B. Atitallah, and J. Dekeyser, Procédé d'optimisation dynamique d'une architecture d'outils de tests système, EP 2482193 (A1), (Number: FR20110000232 20110126), 2011.

M. Rubio, N. Belanger, R. B. Atitallah, and J. Dekeyser, A method of dynamically optimizing an architecture of system test tools. Australian Patent Office, pp.2012200402-2012, 2006.

E. Senn, D. Chillet, O. Zendra, C. Belleudy, R. B. Atitallah et al., Open-people: An open platform for estimation and optimizations of energy consumption, DASIP, 2012.
URL : https://hal.archives-ouvertes.fr/hal-00741609

E. Senn, D. Chillet, O. Zendra, C. Belleudy, S. Bilavarn et al., Open-People: Open Power and Energy Optimization PLatform and Estimator, 2012 15th Euromicro Conference on Digital System Design, 2012.
DOI : 10.1109/DSD.2012.98

URL : https://hal.archives-ouvertes.fr/hal-00664206

O. Souissi, R. B. Atitallah, and A. Artiba, Optimization Of Matching and Scheduling On Heterogeneous CPU/FPGA Architectures, 7th IFAC Conference on Manufacturing Modelling , Management, and Control (IFAC MIM 2013), 2013.
DOI : 10.3182/20130619-3-RU-3018.00196

O. Souissi, R. B. Atitallah, A. Artiba, and S. E. Elmaghraby, Optimization of run-time mapping on heterogeneous cpu/fpga architectures, 9th International Conference of Modeling, Optimization and Simulation -MOSIM'12, 2012.
URL : https://hal.archives-ouvertes.fr/hal-00728644

O. Souissi, R. B. Atitallah, D. Duvivier, A. Artiba, and N. Belanger, Path Planning: A 2013 Survey, International Conference on Industrial Engineering and Systems Management -IESM'2013, 2013.

C. Trabelsi, R. B. Atitallah, S. Meftali, and J. Dekeyser, Model-driven design flow for distributed control in reconfigurable FPGA systems, Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014.
DOI : 10.1109/DASIP.2014.7115631

URL : https://hal.archives-ouvertes.fr/hal-01104617

C. Trabelsi, R. B. Atitallah, S. Meftali, J. Dekeyser, and A. Jemai, A Model-Driven Approach for Hybrid Power Estimation in Embedded Systems Design, EURASIP Journal on Embedded Systems, vol.6, issue.4, pp.10-1155, 2011.
DOI : 10.1109/MS.2003.1231150

URL : https://hal.archives-ouvertes.fr/hal-00784427

V. Viswanathan, R. Ben-atitallah, J. Dekeyser, B. Nakache, and M. Nakache, Dynamic reconfiguration of modular I/O IP cores for avionic applications, 2012 International Conference on Reconfigurable Computing and FPGAs, 2012.
DOI : 10.1109/ReConFig.2012.6416741

V. Viswanathan, R. Ben-atitallah, J. Dekeyser, B. Nakache, and M. Nakache, Redefining the role of fpgas in the next generation avionic systems, Proceedings of the 2014 ACM/SIGDA International Symposium on Field-programmable Gate Arrays, FPGA '14, pp.248-248, 2014.
URL : https://hal.archives-ouvertes.fr/hal-01104615

C. Ababei, Y. Feng, B. Goplen, H. Mogal, T. Zhang et al., Placement and Routing in 3D Integrated Circuits, IEEE Design and Test of Computers, vol.22, issue.6, pp.520-531, 2005.
DOI : 10.1109/MDT.2005.150

N. Abdelli, A. Fouilliart, N. Mien, and E. Senn, High-Level Power Estimation of FPGA, 2007 IEEE International Symposium on Industrial Electronics, pp.925-930, 2007.
DOI : 10.1109/ISIE.2007.4374721

A. Acquaviva, L. Benini, and B. Ricco, Energy characterization of embedded real-time operating systems, Proceedings of the Workshop on Compilers and Operating Systems for Low Power (COLP01), 2001.

G. Afonso, Vers une nouvelle génération de systèmes de test et de simulation avionique dynamiquement reconfigurables, 2013.

G. Afonso, N. Damiani, N. Belanger, R. B. Atitallah, and M. Rubio, Hybrid and multicore optimized architectures for test and simulation systems, Proceedings of the 6th International ICST Conference on Simulation Tools and Techniques, SimuTools '13, 2013.

T. A. Alenawy and H. Aydin, Energy-Aware Task Allocation for Rate Monotonic Scheduling, 11th IEEE Real Time and Embedded Technology and Applications Symposium, pp.213-223, 2005.
DOI : 10.1109/RTAS.2005.20

M. Anis and Y. Massoud, Power design challenges in deep-submicron technology, 2003 46th Midwest Symposium on Circuits and Systems, 2003.
DOI : 10.1109/MWSCAS.2003.1562583

T. Arpinen, E. Salminen, T. D. Hamalainen, and M. Hannikainen, MARTE profile extension for modeling dynamic power management of embedded systems, W6 1st Workshop on Model Based Engineering for Embedded Systems Design, 2010.
DOI : 10.1016/j.sysarc.2011.01.003

T. Asano, Y. Maruyama, and . Yamaguchi, Performance comparison of FPGA, GPU and CPU in image processing, 2009 International Conference on Field Programmable Logic and Applications, 2009.
DOI : 10.1109/FPL.2009.5272532

R. B. Atitallah, S. Niar, and J. Dekeyser, MPSoC power estimation framework at transaction level modeling, 2007 Internatonal Conference on Microelectronics, 2007.
DOI : 10.1109/ICM.2007.4497703

K. Baynes, C. Collins, E. Fiterman, B. Ganesh, P. Kohout et al., The performance and energy consumption of three embedded real-time operating systems, Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems , CASES '01, 2001.
DOI : 10.1145/502217.502253

K. Baynes, C. Collins, E. Fiterman, B. Ganesh, P. Kohout et al., The performance and energy consumption of embedded real-time operating systems, IEEE Transactions on Computers, vol.11, issue.52, pp.1454-1469, 2003.

N. Belanger, J. Bovier, J. Gilot, J. Lebailly, and M. Rubio, Multi-Core computers and PCI Express The future of data acquisition and control systems, ETTC International Conference, 2009.

N. Belanger, N. Favarcq, and Y. Fusero, An Open Real Time Test System Approach, 2009 First International Conference on Advances in System Testing and Validation Lifecycle, 2009.
DOI : 10.1109/VALID.2009.14

N. Belanger and J. Lebailly, Promoting avionic test systems as productivity enablers, The fifth International Conference on Systems, 2010.

G. Beltrame, L. Fossati, and D. Sciuto, ReSP : A Nonintrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.28, issue.12, pp.1857-1869, 2009.

A. D. Benini and L. Bogliolo, System-level dynamic power management, Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pp.23-31, 1999.
DOI : 10.1109/LPD.1999.750384

A. P. Benini and L. Bogliolo, Policy optimization for dynamic power management . Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.18, issue.6, pp.1857-1869, 2002.

L. Benini, E. Flamand, D. Fuin, and D. Melpignano, P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.983-987
DOI : 10.1109/DATE.2012.6176639

P. Benoit, G. Sassatelli, P. Maurine, L. Torres, N. Azemard et al., Towards Autonomous Scalable Integrated Systems, Design Technology for Heterogeneous Embedded Systems, pp.63-89, 2012.
DOI : 10.1007/978-94-007-1125-9_4

URL : https://hal.archives-ouvertes.fr/lirmm-01399454

M. Berekovic, A. Kanstein, B. Mei, and B. D. Sutter, Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor. Microprocessors and Microsystems -Embedded Hardware Design, pp.290-294, 2009.

C. A. , .. A. Bhatti, and M. K. Belleudy, An inter-task real time dvfs scheme for multiprocessor embedded systems, Design and Architectures for Signal and Image Processing 2010 Conference on, pp.136-143, 2011.

K. Bhatti, Energy-aware Scheduling for Multiprocessor Real-time Systems, 2011.
URL : https://hal.archives-ouvertes.fr/tel-00599980

D. G. Bobrow, R. P. Gabriel, and J. L. White, Object-oriented programming. chapter CLOS in Context : The Shape of the Design Space, pp.29-61, 1993.

D. Brooks, V. Tiwari, and M. Martonosi, Wattch : a framework for architectural-level power analysis and optimizations, Proceedings of the 27th annual international symposium on Computer architecture, pp.83-94, 2000.

L. A. Cardona, J. Agrawal, Y. Guo, J. Oliver, and C. Ferrer, Performance-Area Improvement by Partial Reconfiguration for an Aerospace Remote Sensing Application, 2011 International Conference on Reconfigurable Computing and FPGAs, 2009.
DOI : 10.1109/ReConFig.2011.69

A. Cevrero, P. Athanasopoulos, H. Parandeh-afshar, P. Brisk, Y. Lebebici et al., 3D configuration caching for 2D FPGAs, Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays, FPGA '09, pp.286-286, 2009.
DOI : 10.1145/1508128.1508205

C. Chen, B. Lee, and J. Huang, Architectural exploration of 3d fpgas towards a better balance between area and delay, Design, Automation Test in Europe Conference Exhibition (DATE), pp.1-4, 2011.

Y. Chen, The Analysis and Practice on Open Source Embedded System Software?Based on SkyEye and ARM Developing Platform, 2004.

Z. Chen, R. N. Pittman, and A. Forin, Combining multicore and reconfigurable instruction set extensions, Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays, FPGA '10, pp.33-36, 2010.
DOI : 10.1145/1723112.1723119

F. Cloute, J. Contensou, D. Esteve, P. Pampagnin, P. Pons et al., Hardware/software co-design of an avionics communication protocol interface system, Proceedings of the seventh international workshop on Hardware/software codesign , CODES '99, 1999.
DOI : 10.1145/301177.301203

P. Coussy, C. Chavet, P. Bomel, D. Heller, E. Senn et al., GAUT: A High-Level Synthesis Tool for DSP Applications, 2008.
DOI : 10.1007/978-1-4020-8588-8_9

URL : https://hal.archives-ouvertes.fr/hal-00489794

M. F. Da, S. Oliveira, E. W. Brião, F. A. Nascimento, and F. R. Wagner, Model driven engineering for mpsoc design space exploration, SBCCI'07 :Proceedings of the 20th annual conference on Integrated circuits and systems design, 2007.

M. F. Da, S. Oliveira, L. B. De-brisolara, L. Carro, and F. R. Wagner, Early embedded software design space exploration using uml-based estimation, Rapid System Prototyping, 2006.

N. Dhanwada, R. A. Bergamaschi, W. W. Dungan, I. Nair, P. Gramann et al., Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems, Design Automation for Embedded Systems, vol.10, issue.2-3
DOI : 10.1007/s10617-006-9586-7

S. Dhouib, J. Diguet, D. Blouin, and J. Laurent, Energy and Power Consumption Estimation for Embedded Applications and Operating Systems, Journal of Low Power Electronics, vol.5, issue.4, 2009.
DOI : 10.1166/jolpe.2009.1041

URL : https://hal.archives-ouvertes.fr/hal-00429454

C. Dong, D. Chen, S. Tanachutiwat, and W. Wang, Performance and power evaluation of a 3d cmos/nanomaterial reconfigurable architecture, Computer-Aided Design, pp.758-764, 2007.

M. Duranton, D. Black-schaffer, K. De-bosschere, and J. Maebe, HiPEAC network of excellence, THE HIPEAC VISION FOR ADVANCED COMPUTING IN HORIZON, vol.3, p.4, 2013.

D. Elléouet, N. Julien, and D. Houzet, A high level SoC power estimation based on IP modeling, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium, pp.208-208, 2006.
DOI : 10.1109/IPDPS.2006.1639468

D. Elleouet, Y. Savary, and N. Julien, An FPGA Power Aware Design Flow, Power and Timing Modeling, Optimization and Simulation, PATMOS, pp.415-424, 2006.
DOI : 10.1007/11847083_40

URL : https://hal.archives-ouvertes.fr/hal-00437285

H. Esmaeilzadeh, E. Blem, R. St, K. Amant, D. Sankaralingam et al., Dark silicon and the end of multicore scaling, ACM SIGARCH Computer Architecture News, vol.39, issue.3, pp.365-376, 2005.
DOI : 10.1145/2024723.2000108

S. Fuller and L. Millett, Computing Performance: Game Over or Next Level?, Computer, vol.44, issue.1, pp.31-38, 2004.
DOI : 10.1109/MC.2011.15

K. Funaoka, S. Kato, and N. Yamasaki, Energy-Efficient Optimal Real-Time Scheduling on Multiprocessors, 2008 11th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC), pp.23-30, 2008.
DOI : 10.1109/ISORC.2008.19

A. D. , J. L. Danger, and W. P. Burleson, Reducing the power consumption in fpgas with keeping a high performance level. VLSI, IEEE Computer Society Workshop on, p.47, 2000.

A. Garcia, W. Burleson, and J. Danger, Power modelling in field programmable gate arrays (FPGA) Lecture notes in computer science, pp.396-404, 1999.

A. Garcia, W. Burleson, and J. Danger, Power Modelling in Field Programmable Gate Arrays (FPGA), Field Programmable Logic and Applications, pp.396-404, 2004.
DOI : 10.1007/978-3-540-48302-1_44

A. Gayasen, V. Narayanan, M. Kandemir, and A. Rahman, Designing a 3-d fpga : Switch box architecture and thermal issues. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.16, issue.7, pp.882-893, 2008.

D. Gohringer, M. Hubner, V. Schatz, and J. Becker, Runtime adaptive multi-processor system-on-chip: RAMPSoC, 2008 IEEE International Symposium on Parallel and Distributed Processing, 2008.
DOI : 10.1109/IPDPS.2008.4536503

M. Gries and K. Keutzer, Building ASIPs : The Mescal Methodology, 2005.
DOI : 10.1007/b136892

A. Jacobs, G. Cieslewski, A. D. George, A. Gordon-ross, and H. Lam, Reconfigurable Fault Tolerance, ACM Transactions on Reconfigurable Technology and Systems, vol.5, issue.4, pp.1-2130, 2012.
DOI : 10.1145/2392616.2392619

A. B. Kahng, The ITRS design technology and system drivers roadmap, Proceedings of the 50th Annual Design Automation Conference on, DAC '13, pp.1-34, 2013.
DOI : 10.1145/2463209.2488776

R. S. Choi, W. Lee, and L. A. , Massoud Pedram Department of EE- Systems, University of Southern California. Dynamic voltage and frequency scaling under a precise energy model considering variable and fixed components of the system power dissipation

H. Krichene, M. Baklouti, M. Abid, P. Marquet, and J. Dekeyser, Broadcast with mask on a massively parallel processing on a chip, 2012 International Conference on High Performance Computing & Simulation (HPCS), 2012.
DOI : 10.1109/HPCSim.2012.6266924

URL : https://hal.archives-ouvertes.fr/hal-00688418

S. Kumar-rethinagiri, System-level power estimation methodology for MPSoC based platforms, 2013.

M. Lanuzza, P. Zicari, F. Frustaci, S. Perri, and P. Corsonello, Exploiting selfreconfiguration capability to improve sram-based fpga robustness in space and avionics applications, ACM Trans. Reconfigurable Technol. Syst, vol.4, issue.1, 2010.

J. Laurent, N. Julien, and E. Martin, Softexplorer : estimation, characterization and optimization of the power and energy consumption at the algorithmic level, Fourteenth International Workshop on Power and Timing Modeling, pp.15-17, 2004.
URL : https://hal.archives-ouvertes.fr/hal-00013977

J. Laurent, N. Julien, E. Senn, and E. Martin, Functional level power analysis: an efficient approach for modeling the power consumption of complex processors, Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004.
DOI : 10.1109/DATE.2004.1268921

URL : https://hal.archives-ouvertes.fr/hal-00013979

I. Lee, H. Kim, P. Yang, S. Yoo, E. Chung et al., P, Proceedings of the 2006 conference on Asia South Pacific design automation , ASP-DAC '06, 2006.
DOI : 10.1145/1118299.1118431

URL : https://hal.archives-ouvertes.fr/jpa-00224550

M. Lin, A. Gamal, Y. Lu, and S. Wong, Performance benefits of monolithically stacked 3D-FPGA, Proceedings of the internation symposium on Field programmable gate arrays , FPGA'06, pp.113-122, 2006.
DOI : 10.1145/1117201.1117219

M. Lin, A. Gamal, Y. Lu, and S. Wong, Performance benefits of monolithically stacked 3D-FPGA, Proceedings of the internation symposium on Field programmable gate arrays , FPGA'06, pp.113-122, 2006.
DOI : 10.1145/1117201.1117219

F. Liu, F. Guo, Y. Solihin, S. Kim, and A. Eker, Characterizing and modeling the behavior of context switch misses, Proceedings of the 17th international conference on Parallel architectures and compilation techniques, PACT '08, pp.91-101, 2008.
DOI : 10.1145/1454115.1454130

P. Marquet, S. Duquennoy, S. L. Beux, S. Meftali, and J. Dekeyser, Massively parallel processing on a chip, Proceedings of the 4th international conference on Computing frontiers , CF '07, pp.277-286, 2007.
DOI : 10.1145/1242531.1242571

URL : https://hal.archives-ouvertes.fr/hal-00688418

N. Dhanwada, I. Lin, and V. Narayanan, A power estimation methodology for systemC transaction level models, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS '05, 2005.
DOI : 10.1145/1084834.1084874

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.92.3172

F. Nicolas, F. Antoine, and F. Paul, esimu : a fast and accurate energy consumption simulator for real embedded system, IEEE International Symposium on a World of Wireless, Mobile and Multimedia Networks, pp.1-6, 2007.

B. Osterloh, H. Michalik, S. Habinc, and B. Fiethe, Dynamic Partial Reconfiguration in Space Applications, 2009 NASA/ESA Conference on Adaptive Hardware and Systems, 2009.
DOI : 10.1109/AHS.2009.13

J. Park, D. Shin, N. Chang, and M. Pedram, Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors, Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design, ISLPED '10, pp.419-424, 2010.
DOI : 10.1145/1840845.1840938

K. D. Pham, A. Jain, J. Cui, S. Fahmy, and D. Maskell, Microkernel hypervisor for a hybrid arm-fpga platform, Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE 24th International Conference on, pp.219-226, 2013.

E. Philips, T. Design, and . Group, DIESEL User Manual, 2001.

S. Project, An open platform for modelling and simulation of multi-processors system on chip

M. Reserach, emips : a dynamically extensible processor, 2006.

S. Rethinagiri, R. B. Atitallah, S. Niar, E. Senn, and J. Dekeyser, Hybrid system level power consumption estimation for FPGA-based MPSoC, 2011 IEEE 29th International Conference on Computer Design (ICCD), pp.239-246, 2011.
DOI : 10.1109/ICCD.2011.6081403

URL : https://hal.archives-ouvertes.fr/hal-00842401

J. D. Douhib, Model driven high-level power estimation of embedded operating systems communication and synchronization services, Proceedings of the 6th IEEE International Conference on Embedded Software and Systems, China, 2009.
URL : https://hal.archives-ouvertes.fr/hal-00489833

R. G. Irani and S. Shukla, Competitive analysis of dynamic power management strategies for systems with multiple power saving states, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, p.117, 2002.
DOI : 10.1109/DATE.2002.998258

D. Sacchetto, M. Zervas, Y. Temiz, G. De-micheli, and Y. Leblebici, Resistive Programmable Through-Silicon Vias for Reconfigurable 3-D Fabrics, IEEE Transactions on Nanotechnology, vol.11, issue.1, pp.8-11, 2012.
DOI : 10.1109/TNANO.2011.2160557

E. Senn, N. Julien, N. Abdelli, D. Elleouet, and Y. Savary, Building and using system, algorithmic, and architectural power and energy models in the fpga design-flow, Intl. Conf. on Reconfigurable Communication-centric SoCs, 2006.
URL : https://hal.archives-ouvertes.fr/hal-00083353

D. Shin and J. Kim, Intra-task voltage scheduling on DVS-enabled hard real-time systems . Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.24, issue.10, pp.1530-1549, 2005.

D. Shin and J. Kim, Fine-grained DVFS using on-chip regulators. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.8, 2011.

S. K. Shukla and R. K. Gupta, A model checking approach to evaluating system level dynamic power management policies for embedded systems, Sixth IEEE International High-Level Design Validation and Test Workshop, p.53, 2001.
DOI : 10.1109/HLDVT.2001.972807

H. Sidiropoulos, K. Siozios, and D. Soudris, A novel 3-D FPGA architecture targeting communication intensive applications, Journal of Systems Architecture, vol.60, issue.1, pp.32-39
DOI : 10.1016/j.sysarc.2013.09.012

K. Siozios, V. F. Pavlidis, and D. Soudris, A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric, ACM Transactions on Reconfigurable Technology and Systems, vol.5, issue.1, p.4, 2012.
DOI : 10.1145/2133352.2133356

L. Sterpone, F. Margaglia, M. Koester, J. Hagemeyer, and M. Porrmann, Analysis of SEU effects in partially reconfigurable SoPCs, 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2009.
DOI : 10.1109/AHS.2011.5963926

V. Tiwari, S. Malik, and A. Wolfe, Power analysis of embedded software : A first step towards software power minimization, Transactions on VLSI Systems, 1994.

N. Tredennick and B. Shimamoto, The Inevitability of Reconfigurable Systems, Queue, vol.1, issue.7, pp.34-43, 2003.
DOI : 10.1145/957717.957767

D. Tsafrir, The context-switch overhead inflicted by hardware interrupts (and the enigma of do-nothing loops), Proceedings of the 2007 workshop on Experimental computer science, ExpCS '07, 2007.
DOI : 10.1145/1281700.1281704

J. R. Villarreal, A. Park, W. A. Najjar, and R. Halstead, Designing Modular Hardware Accelerators in C with ROCCC 2.0, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, pp.2-4, 2010.
DOI : 10.1109/FCCM.2010.28

J. R. Villarreal, A. Park, W. A. Najjar, and R. Halstead, Designing Modular Hardware Accelerators in C with ROCCC 2.0, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, pp.2-4, 2010.
DOI : 10.1109/FCCM.2010.28

W. Wolf, A. Jerraya, and G. Martin, Multiprocessor system-on-chip (mpsoc) technology . Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.27, issue.10 4, pp.1701-1713, 2008.
DOI : 10.1109/tcad.2008.923415

W. Ye, N. Vijaykrishnan, M. Kandemir, and M. Irwin, The Design and Use of Simple- Power : A Cycle Accurate Energy Estimation Tool, Design Automation Conf, 2000.

P. Yuh, C. Yang, C. Li, and C. Lin, Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs, ACM Transactions on Design Automation of Electronic Systems, vol.14, issue.4, pp.1-26, 2009.
DOI : 10.1145/1562514.1562520

X. Zhao, Y. Guo, H. Wang, and X. Chen, Fine-Grained Energy Estimation and Optimization of Embedded Operating Systems, 2008 International Conference on Embedded Software and Systems Symposia, pp.90-95, 2008.
DOI : 10.1109/ICESS.Symposia.2008.58

W. H. Zheng, N. Marzwell, and S. Chau, In-System Partial Run-Time Reconfiguration for Fault Recovery Applications on Spacecrafts, 2005 IEEE International Conference on Systems, Man and Cybernetics, pp.3952-3957, 2005.
DOI : 10.1109/ICSMC.2005.1571763