M. Défnitions, 56 3.2.1. Environnement de calcul, p.57

P. Défnition-du, 59 3.3.2, p.62

D. Forray, Du Walkman à l'iPod, 30 ans de balade, 2009.

/. Availablee-htpe and . Www, du-walkman-a-lipod-30-ans-de-balade, 2014.

M. Desmurget, Les conséquences que le temps fou passé devant des écrans a sur le cerveau, 2014.

S. Saponara, K. Denolf, G. Lafruit, C. Blanch, and J. Bormans, Performance and Complexity Co-evaluation of the Advanced Video Coding Standard for Cost-Efective Multimedia Communications, EURASIP J. Adv. Signal Process, vol.2004, issue.2, p.2144371, 2004.

J. Ohm, G. J. Sullivan, H. Schwarz, T. K. Tan, and T. Wiegand, Comparison of the Coding Efficiency of Video Coding Standards—Including High Efficiency Video Coding (HEVC), IEEE Transactions on Circuits and Systems for Video Technology, vol.22, issue.12, pp.1669-1684, 2012.
DOI : 10.1109/TCSVT.2012.2221192

J. Gorin, M. Raulet, and F. Prêteux, MPEG Reconfgurable Video CodingE From specifcation to a reconfgurable implementation Signal Process, Image Commun, vol.28, issue.10, pp.1224-1238, 2013.

A. Salkintzis and N. Passas, Emerging Wireless Multimedia: Services and Technologies, 2005.
DOI : 10.1002/0470021519

I. E. Richardson and H. , 264 and MPEG-4 video compression: video coding for next generation multimedia, Chichesterf Hoboken, 2003.
DOI : 10.1002/0470869615

A. K. Khan and H. Jamal, Te Intra Prediction in H, Novel Algorithms and Techniques In Telecommunications, Automation and Industrial Electronics

S. Wang, T. Lin, T. Liu, and C. Lee, A new motion compensation design for H.264/AVC decoder, IEEE International Symposium on Circuits and Systems, pp.4558-4561, 2005.

M. Samek, CONTRIBUTING EDITORS-Te Embedded Angle-Te Embedded Mindset-Innovation in skinning the Heap Cat, CC Users J, pp.39-45, 2003.

J. L. Hennessy, Computer Architecture, Fifh Edition: A Qantitative Approach, 5 edition, 2011.

W. Sheng, S. Schürmans, M. Odendahl, M. Bertsch, V. Volevach et al., A compiler infrastructure for embedded heterogeneous MPSoCs, Parallel Computing, vol.40, issue.2, pp.51-68, 2014.
DOI : 10.1016/j.parco.2013.11.007

J. R. Levine, Linkers and Loaders, 1999.

U. Drepper, How to write shared libraries, 2006.

F. Yazdanpanah, C. Alvarez-martinez, D. Jimenez-gonzalez, and Y. Etsion, Hybrid Datafow/von-Neumann Architectures, IEEE Trans. Parallel Distrib. Syst, vol.25, issue.6, p.pp
DOI : 10.1109/tpds.2013.125

M. Dehyadegari, A. Marongiu, M. R. Kakoee, L. Benini, S. Mohammadi et al., A tightly-coupled multi-core cluster with shared-memory HW accelerators, 2012 International Conference on Embedded Computer Systems (SAMOS), pp.96-103
DOI : 10.1109/SAMOS.2012.6404162

P. Chen, L. Zhang, Y. Han, and Y. Chen, A General-Purpose Many-Accelerator Architecture Based on Dataflow Graph Clustering of Applications, Journal of Computer Science and Technology, vol.26, issue.1, pp.239-246, 2014.
DOI : 10.1007/s11390-014-1426-9

M. Mishra, T. J. Callahan, T. Chelcea, G. Venkataramani, S. C. Goldstein et al., TartanE Evaluating Spatial Computation for Whole Program Execution, Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, pp.163-174, 2006.

V. Govindaraju, C. Ho, T. Nowatzki, J. Chhugani, N. Satish et al., DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing, IEEE Micro, vol.32, issue.5, pp.38-51, 2012.
DOI : 10.1109/MM.2012.51

J. B. Dennis, First version of a data fow procedure language, Programming Symposium, pp.362-376, 1974.

E. Lee, Consistency in dataflow graphs, IEEE Transactions on Parallel and Distributed Systems, vol.2, issue.2, pp.223-235, 1991.
DOI : 10.1109/71.89067

T. M. Parks, Bounded scheduling of process networks, 1995.

S. A. Neuendorfer, Actor-oriented metaprogramming, 2005.

B. Bhatacharya and S. S. Bhatacharyya, Parameterized dataflow modeling for DSP systems, IEEE Transactions on Signal Processing, vol.49, issue.10, pp.2408-2421, 2001.
DOI : 10.1109/78.950795

P. Fradet, A. Girault, and P. Poplavkoy, SPDFE A schedulable parametric data-fow MoC, Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.769-774, 2012.

V. Bebelis, P. Fradet, A. Girault, and B. Lavigueur, BPDFE A statically analyzable datafow model with integer and boolean parameters, 2013 Proceedings of the International Conference on Embedded Sofware (EMSOFT), pp.1-10, 2013.

J. T. Buck and E. A. Lee, Scheduling dynamic datafow graphs with bounded memory using the token fow model, Acoustics, Speech, and Signal Processing IEEE International Conference on, pp.429-432, 1993.

J. T. Buck, Static scheduling and code generation from dynamic datafow graphs with integer-valued control streams, 1994 Conference Record of the Twenty-Eighth Asilomar Conference on Signals, Systems and Computers, pp.508-513, 1994.
DOI : 10.1109/acssc.1994.471505

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

G. Kahn, Te Semantics of a Simple Language for Parallel Programming, Information Processing '74: Proceedings of the IFIP Congress, pp.471-475, 1974.

E. A. Lee and D. G. Messerschmit, Synchronous data fow, Proc. IEEE, pp.1235-1245, 1987.

G. Bilsen, M. Engels, R. Lauwereins, and J. Peperstraete, Cycle-static dataflow, IEEE Transactions on Signal Processing, vol.44, issue.2, pp.397-408, 1996.
DOI : 10.1109/78.485935

S. Stuijk, Predictable mapping of streaming applications on multiprocessors, 2007.

M. Geilen and T. Basten, Requirements on the Execution of Kahn Process Networks, Programming languages and systems, pp.319-334, 2003.
DOI : 10.1007/3-540-36575-3_22

G. E. Allen, P. E. Zucknick, and B. L. Evans, A Distributed Deadlock Detection and Resolution Algorithm for Process Networks, 2007 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '07, pp.33-36, 2007.
DOI : 10.1109/ICASSP.2007.366165

B. Jiang, E. Depretere, and B. Kienhuis, Hierarchical run time deadlock detection in process networks, 2008 IEEE Workshop on Signal Processing Systems, pp.239-244, 2008.
DOI : 10.1109/SIPS.2008.4671769

A. G. Olson and B. L. Evans, Deadlock Detection For Distributed Process Networks, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005., p.73, 2005.
DOI : 10.1109/ICASSP.2005.1416243

E. L. Lawler, J. K. Lenstra, A. H. Kan, and D. B. Shmoys, Chapter 9 Sequencing and scheduling: Algorithms and complexity, Handb. Oper. Res. Manag. Sci, vol.4, pp.445-522, 1993.
DOI : 10.1016/S0927-0507(05)80189-6

E. A. Lee and S. Ha, Scheduling strategies for multiprocessor real-time DSP, IEEE Global Telecommunications Conference, 1989, and Exhibition. 'Communications Technology for the 1990s and Beyond, pp.1279-1283, 1989.
DOI : 10.1109/GLOCOM.1989.64160

H. Topcuoglu, S. Hariri, and M. Wu, Performance-effective and low-complexity task scheduling for heterogeneous computing, IEEE Transactions on Parallel and Distributed Systems, vol.13, issue.3, pp.260-274, 2002.
DOI : 10.1109/71.993206

T. L. Adam, K. M. Chandy, and J. R. Dickson, A comparison of list schedules for parallel processing systems, Communications of the ACM, vol.17, issue.12, pp.685-690, 1974.
DOI : 10.1145/361604.361619

S. Ha, Compile-time scheduling of datafow program graphs with dynamic constructs, 1992.

L. Canon, E. Jeannot, R. Sakellariou, and W. Zheng, Comparative Evaluation Of The Robustness Of DAG Scheduling Heuristics, Grid Computing, pp.73-84, 2008.
DOI : 10.1007/978-0-387-09457-1_7

URL : https://hal.archives-ouvertes.fr/inria-00333903

Z. Shi and J. J. Dongarra, Scheduling workflow applications on processors with different capabilities, Future Generation Computer Systems, vol.22, issue.6, pp.665-675, 2006.
DOI : 10.1016/j.future.2005.11.002

H. Arabnejad and J. G. Barbosa, List Scheduling Algorithm for Heterogeneous Systems by an Optimistic Cost Table, IEEE Transactions on Parallel and Distributed Systems, vol.25, issue.3, pp.682-694, 2014.
DOI : 10.1109/TPDS.2013.57

G. C. Sih and E. A. Lee, A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architectures, IEEE Transactions on Parallel and Distributed Systems, vol.4, issue.2, pp.175-187, 1993.
DOI : 10.1109/71.207593

R. Sethi, Complete Register Allocation Problems, SIAM Journal on Computing, vol.4, issue.3, pp.226-248, 1975.
DOI : 10.1137/0204020

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

P. Briggs, Register allocation via graph coloring, Rice University, 1992.

G. Chaitin, Register allocation and spilling via graph coloring, ACM SIGPLAN Notices, vol.39, issue.4, pp.66-74, 2004.
DOI : 10.1145/989393.989403

A. Batat and D. G. Feitelson, Gang scheduling with memory considerations, Proceedings 14th International Parallel and Distributed Processing Symposium. IPDPS 2000, pp.109-114, 2000.
DOI : 10.1109/IPDPS.2000.845971

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

J. W. Liu, On the storage requirement in the out-of-core multifrontal method for sparse factorization, ACM Transactions on Mathematical Software, vol.12, issue.3, pp.249-264, 1986.
DOI : 10.1145/7921.11325

L. Marchal, O. Sinnen, and F. Vivien, Scheduling Tree-Shaped Task Graphs to Minimize Memory and Makespan, 2013 IEEE 27th International Symposium on Parallel and Distributed Processing, pp.839-850, 2013.
DOI : 10.1109/IPDPS.2013.55

URL : https://hal.archives-ouvertes.fr/hal-00740105

J. Herrmann, L. Marchal, and Y. Robert, Memory-Aware List Scheduling for Hybrid Platforms, 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014.
DOI : 10.1109/IPDPSW.2014.80

URL : https://hal.archives-ouvertes.fr/hal-00944336

T. P. Baker, Stack-based scheduling of realtime processes, Real-Time Systems, vol.1, issue.3, pp.67-99, 1991.
DOI : 10.1007/BF00365393

J. Gilbert, T. Lengauer, and R. Tarjan, The Pebbling Problem is Complete in Polynomial Space, SIAM Journal on Computing, vol.9, issue.3, pp.513-524, 1980.
DOI : 10.1137/0209038

I. Auge, F. Petrot, F. Donnet, and P. Gomez, Platform-based design from parallel C specifications, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.24, issue.12, pp.1811-1826, 2005.
DOI : 10.1109/TCAD.2005.852431

URL : https://hal.archives-ouvertes.fr/hal-00017411

H. Yviquel, A. Lorence, K. Jerbi, G. Cocherel, A. Sanchez et al., OrccE Multimedia Development Made Easy, Proceedings of the 21st ACM International Conference on Multimedia, pp.863-866, 2013.

M. Wipliez, G. Roquier, and J. Nezan, Software Code Generation for the RVC-CAL Language, Journal of Signal Processing Systems, vol.29, issue.12, pp.203-213, 2009.
DOI : 10.1007/s11265-009-0390-z

URL : https://hal.archives-ouvertes.fr/hal-00407950

J. Castrillon, R. Leupers, and G. Ascheid, MAPS: Mapping Concurrent Dataflow Applications to Heterogeneous MPSoCs, IEEE Transactions on Industrial Informatics, vol.9, issue.1, pp.527-545, 2013.
DOI : 10.1109/TII.2011.2173941

L. Ferro, Vérifcation de propriétés logico-temporelles de spécifcations SystemC TLM, 2011.

A. Mello, I. Maia, A. Greiner, and F. Pecheux, Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pp.606-609, 2010.
DOI : 10.1109/DATE.2010.5457136

URL : https://hal.archives-ouvertes.fr/hal-00748083

M. H. Wiggers, M. J. Bekooij, and G. J. Smit, Monotonicity and run-time scheduling, Proceedings of the seventh ACM international conference on Embedded software, EMSOFT '09, pp.177-186, 2009.
DOI : 10.1145/1629335.1629359

URL : http://eprints.eemcs.utwente.nl/19113/01/poster_bears2010.pdf

H. Lee, W. Che, and K. Chatha, Dynamic scheduling of stream programs on embedded multi-core processors, Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS '12, pp.93-102, 2012.
DOI : 10.1145/2380445.2380465

E. Garcia, D. Orozco, R. Pavel, and G. R. Gao, A Discussion in Favor of Dynamic Scheduling for Regular Applications in Many-core Architectures, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum, pp.1591-1600, 2012.
DOI : 10.1109/IPDPSW.2012.200

Z. Zhou, K. Desnos, M. Pelcat, J. Nezan, W. Plishker et al., Scheduling of parallelized synchronous datafow actors, 2013 International Symposium on System on Chip (SoC), pp.1-10, 2013.

G. Liu, Y. He, L. Guo, and F. Qi, Static Scheduling of Synchronous Data Flow onto Multiprocessors for Embedded DSP Systems, 2011 Third International Conference on Measuring Technology and Mechatronics Automation, pp.338-341, 2011.
DOI : 10.1109/ICMTMA.2011.655

J. Falk, J. Keinert, C. Haubelt, J. Teich, and S. S. Bhatacharyya, A generalized static data fow clustering algorithm for mpsoc scheduling of multimedia applications, Proceedings of the 8th ACM international conference on Embedded sofware, pp.189-198, 2008.

A. Sbîrlea, Y. Zou, Z. Budimlíc, J. Cong, and V. Sarkar, Mapping a Data-fow Programming Model Onto Heterogeneous Platforms, Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Teory for Embedded Systems, pp.61-70

H. Wu, C. Shen, N. Sane, W. Plishker, and S. S. Bhatacharyya, A Model-Based Schedule Representation for Heterogeneous Mapping of Datafow Graphs, pp.70-81, 2011.

J. Boutellier, C. Lucarz, V. M. Gomez, M. Matavelli, and O. Silvén, Multiprocessor Scheduling of Datafow Programs within the Reconfgurable Video Coding Framework, Algorithm-Architecture Matching for Signal and Image Processing, pp.237-251, 2011.

H. Yviquel, E. Casseau, M. Wipliez, and M. Raulet, Efcient multicore scheduling of datafow process networks, Signal Processing Systems (SiPS), pp.198-203, 2011.

H. Yviquel, E. Casseau, M. Raulet, P. Jaaskelainen, and J. Takala, Towards run-time actor mapping of dynamic datafow programs onto multi-core platforms, 2013 8th International Symposium on Image and Signal Processing and Analysis (ISPA), pp.732-737, 2013.

H. Yviquel, A. Sanchez, P. Jaaskelainen, J. Takala, M. Raulet et al., Efcient sofware synthesis of dynamic datafow programs, 2014 IEEE International Conference on Acoustics, Speech and Signal Processing, pp.2014-4988

L. Lamport, Specifying Concurrent Program Modules, ACM Transactions on Programming Languages and Systems, vol.5, issue.2, pp.190-222, 1983.
DOI : 10.1145/69624.357207

J. Heulot, J. Boutellier, M. Pelcat, J. Nezan, and S. Aridhi, Applying the adaptive Hybrid Flow-Shop scheduling method to schedule a 3GPP LTE physical layer algorithm onto many-core digital signal processors, 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013), pp.123-129, 2013.
DOI : 10.1109/AHS.2013.6604235

URL : https://hal.archives-ouvertes.fr/hal-00877643

H. Kee, S. S. Bhatacharyya, I. Wong, and Y. Rao, FPGA-based design and implementation of the 3GPP-LTE physical layer using parameterized synchronous datafow techniques, IEEE International Conference on Acoustics, Speech and Signal Processing -Proceedings, pp.1510-1513, 2010.

J. Epstein, Te Yale Book of Qotations, 2006.

M. Wipliez, Infrastructure de compilation pour des programmes fux de données, INSA de Rennes, 2010.

M. Matavelli, I. Amer, and M. Raulet, The Reconfigurable Video Coding Standard [Standards in a Nutshell, IEEE Signal Processing Magazine, vol.27, issue.3, pp.159-167, 2010.
DOI : 10.1109/MSP.2010.936032

I. Richardson, White Paper: An Overview of H. 264 Advanced Video Coding. Vcodex, 2007.