Y. Chen and P. Hsiung, Hardware Task Scheduling and Placement in Operating Systems for Dynamically Reconfigurable SoC, Embedded and Ubiquitous Computing?EUC 2005, pp.489-498, 2005.
DOI : 10.1007/11596356_50

V. Tong, The evolution of 3d ics leaping ahead of moore's law to deliver a 6.8b transistor device. SiP Global Summit, 2012.

Q. Khuat, Q. Le, D. Chillet, and S. Pillement, Spatiotemporal scheduling for 3d reconfigurable & multiprocessor architecture, 8th International Design and Test Symposium (IDT), pp.1-6, 2013.
URL : https://hal.archives-ouvertes.fr/hal-00741578

T. Marconi, Y. Lu, K. Bertels, and G. Gaydadjiev, A novel fast online placement algorithm on 2D partially reconfigurable devices, 2009 International Conference on Field-Programmable Technology, pp.296-299, 2009.
DOI : 10.1109/FPT.2009.5377661

H. Quang, D. Khuat, and . Chillet, Communication cost reduction for hardware tasks placed on homogeneous reconfigurable resource, International Conference on Design and Architectures for Signal and Image Processing (DASIP), pp.265-270, 2013.

Q. Khuat, D. Chillet, and M. Hubner, Considering reconfiguration overhead in scheduling of dependent tasks on 2D reconfigurable FPGA, 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp.1-8, 2014.
DOI : 10.1109/AHS.2014.6880151

URL : https://hal.archives-ouvertes.fr/hal-01097496

Q. H. Quang-hai-khuat, D. Le, A. Chillet, E. Courtay, and . Casseau, Ordonnancement spatio-temporel 3d minimisant le coût de communications entre tâches, GRETSI 2013, pp.1-7, 2013.

Q. Khuat, D. Chillet, and M. Hubner, Dynamic run-time hardware/software scheduling for 3D reconfigurable SoC, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14), 2014.
DOI : 10.1109/ReConFig.2014.7032512

URL : https://hal.archives-ouvertes.fr/hal-01097509

Y. Joseph, J. Leung, and . Whitehead, On the complexity of fixed-priority scheduling of periodic, real-time tasks. Performance evaluation, pp.237-250, 1982.

C. Laung, L. James, and W. Layland, Scheduling algorithms for multiprogramming in a hard-real-time environment, Journal of the ACM (JACM), vol.20, issue.1, pp.46-61, 1973.

K. Aloysius and . Mok, Fundamental design problems of distributed systems for the hardreal-time environment, 1983.

K. Kavi, R. Akl, and A. Hurson, Real-Time Systems: An Introduction and the State-of-the-Art, 2008.
DOI : 10.1002/9780470050118.ecse344

M. John, . Calandrino, H. James, D. P. Anderson, and . Baumberger, A hybrid realtime scheduling approach for large-scale multicore platforms, Real-Time Systems, 2007. ECRTS'07. 19th Euromicro Conference on, pp.247-258, 2007.

K. Sanjoy, . Baruah, K. Neil, G. Cohen, . Plaxton et al., Proportionate progress: A notion of fairness in resource allocation, Algorithmica, vol.15, issue.6, pp.600-625, 1996.

G. Levin, S. Funk, C. Sadowski, I. Pye, and S. Brandt, DP-FAIR: A Simple Model for Understanding Optimal Multiprocessor Scheduling, 2010 22nd Euromicro Conference on Real-Time Systems, pp.3-13, 2010.
DOI : 10.1109/ECRTS.2010.34

X. Qi, D. Zhu, and H. Aydin, A Study of Utilization Bound and Run-Time Overhead for Cluster Scheduling in Multiprocessor Real-Time Systems, 2010 IEEE 16th International Conference on Embedded and Real-Time Computing Systems and Applications, pp.3-12, 2010.
DOI : 10.1109/RTCSA.2010.15

G. Umarani-srikanth, . Shanthi, A. Maheswari, and . Siromoney, A survey on real time task scheduling, European Journal of Scientific Research, vol.69, issue.1, pp.33-41, 2012.

T. Lodewijk, J. L. Smit, . Hurink, J. Gerard, and . Smit, Run-time mapping of applications to a heterogeneous soc, 2005.

A. Kumar-singh, T. Srikanthan, A. Kumar, and W. Jigang, Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms, Journal of Systems Architecture, vol.56, issue.7, pp.242-255, 2010.
DOI : 10.1016/j.sysarc.2010.04.007

S. Murali, M. Coenen, A. Radulescu, K. Goossens, and G. D. Micheli, A Methodology for Mapping Multiple Use-Cases onto Networks on Chips, Proceedings of the Design Automation & Test in Europe Conference, pp.118-123, 2006.
DOI : 10.1109/DATE.2006.244007

H. Orsila, T. Kangas, E. Salminen, D. Timo, M. Hämäläinen et al., Automated memory-aware application distribution for Multi-processor System-on-Chips, Journal of Systems Architecture, vol.53, issue.11, pp.53795-815, 2007.
DOI : 10.1016/j.sysarc.2007.01.013

F. Ferrandi, P. L. Lanzi, C. Pilato, D. Sciuto, and A. Tumeo, Ant colony heuristic for mapping and scheduling tasks and communications on heterogeneous embedded systems. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.29, issue.6, pp.911-924, 2010.

D. Buell, T. El-ghazawi, K. Gaj, and V. Kindratenko, Guest Editors' Introduction: High-Performance Reconfigurable Computing, Computer, vol.40, issue.3, p.23, 2007.
DOI : 10.1109/MC.2007.91

E. Horta, W. John, and . Lockwood, Parbit: a tool to transform bitfiles to implement partial reconfiguration of field programmable gate arrays (fpgas)

H. Kalte, G. Lee, M. Porrmann, and U. Ruckert, REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems, 19th IEEE International Parallel and Distributed Processing Symposium, pp.151-151, 2005.
DOI : 10.1109/IPDPS.2005.380

H. Kalte and M. Porrmann, REPLICA2Pro, Proceedings of the 3rd conference on Computing frontiers , CF '06, pp.403-412, 2006.
DOI : 10.1145/1128022.1128045

S. Corbetta, M. Morandi, M. Novati, D. Marco, D. Santambrogio et al., Internal and external bitstream relocation for partial dynamic reconfiguration. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.17, issue.11, pp.1650-1654, 2009.

M. Touiza, G. Ochoa-ruiz, E. Bourennane, A. Guessoum, and K. Messaoudi, A novel methodology for accelerating bitstream relocation in partially reconfigurable systems, Microprocessors and Microsystems, vol.37, issue.3, pp.358-372, 2013.
DOI : 10.1016/j.micpro.2012.07.004

URL : https://hal.archives-ouvertes.fr/hal-00730221

K. Danne and M. Platzner, Periodic real-time scheduling for fpga computers, Intelligent Solutions in Embedded Systems, 2005. Third International Workshop on, pp.117-127, 2005.

F. Redaelli, D. Marco, . Santambrogio, and . Memik, An ilp formulation for the task graph scheduling problem tailored to bi-dimensional reconfigurable architectures, International Journal of Reconfigurable Computing, 2009.

J. Resano, D. Mozos, and F. Catthoor, A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware, Design, Automation and Test in Europe, pp.106-111, 2005.
DOI : 10.1109/DATE.2005.18

URL : https://hal.archives-ouvertes.fr/hal-00181666

Y. Qu, J. Soininen, and J. Nurmi, A parallel configuration model for reducing the run-time reconfiguration overhead, Proceedings of the conference on Design, automation and test in Europe: Proceedings European Design and Automation Association, pp.965-969, 2006.

Y. Lu, T. Marconi, K. Bertels, and G. Gaydadjiev, A Communication Aware Online Task Scheduling Algorithm for FPGA-Based Partially Reconfigurable Systems, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, pp.65-68, 2010.
DOI : 10.1109/FCCM.2010.18

P. Mahr and C. Bobda, Reducing communication costs on Dynamic Networks-on-Chip through runtime relocation of tasks, 2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP), pp.177-182, 2012.
DOI : 10.1109/RSP.2012.6380708

D. Göhringer, M. Hübner, E. N. Zeutebouo, and J. Becker, Operating System for Runtime Reconfigurable Multiprocessor Systems, International Journal of Reconfigurable Computing, vol.2011, issue.3, 2011.
DOI : 10.1155/ES/2006/56320

C. Steiger, H. Walder, and M. Platzner, Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices, Field Programmable Logic and Application, pp.575-584, 2003.
DOI : 10.1007/978-3-540-45234-8_56

C. Steiger, H. Walder, and M. Platzner, Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks, IEEE Transactions on Computers, vol.53, issue.11, pp.1393-1407, 2004.
DOI : 10.1109/TC.2004.99

M. Hubner, C. Schuck, and J. Becker, Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium, p.8, 2006.
DOI : 10.1109/IPDPS.2006.1639449

K. Bazargan, R. Kastner, and M. Sarrafzadeh, Fast template placement for reconfigurable computing systems, IEEE Design & Test of Computers, vol.17, issue.1, pp.68-83, 2000.
DOI : 10.1109/54.825678

M. Handa and R. Vemuri, An efficient algorithm for finding empty space for online FPGA placement, Proceedings of the 41st annual conference on Design automation , DAC '04, pp.960-965, 2004.
DOI : 10.1145/996566.996820

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.4.8092

J. Cui, Q. Deng, X. He, and Z. Gu, An Efficient Algorithm for Online Management of 2D Area of Partially Reconfigurable FPGAs, 2007 Design, Automation & Test in Europe Conference & Exhibition, pp.129-134, 2007.
DOI : 10.1109/DATE.2007.364579

Y. Lu, T. Marconi, G. Gaydadjiev, and K. Bertels, An efficient algorithm for free resources management on the fpga, Proceedings of the conference on Design, automation and test in Europe, pp.1095-1098, 2008.

A. Ahmadinia, C. Bobda, M. Bednara, and J. Teich, A new approach for on-line placement on reconfigurable devices, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings., p.134, 2004.
DOI : 10.1109/IPDPS.2004.1303104

L. Wei, D. Zhang, and Q. Chen, A least wasted first heuristic algorithm for the rectangular packing problem, Computers & Operations Research, vol.36, issue.5, pp.1608-1614, 2009.
DOI : 10.1016/j.cor.2008.03.004

J. Tabero, J. Septién, H. Mecha, and D. Mozos, Allocation heuristics and defragmentation measures for reconfigurable systems management, Integration, the VLSI Journal, vol.41, issue.2, pp.281-296, 2008.
DOI : 10.1016/j.vlsi.2007.08.001

S. Olakkenghil and K. Baskaran, An FPGA Task Placement Algorithm Using Reflected Binary Gray Space Filling Curve, International Journal of Reconfigurable Computing, vol.2014, 2014.
DOI : 10.1109/TC.2004.99

URL : http://doi.org/10.1155/2014/495080

M. Koester, M. Porrmann, and H. Kalte, Task placement for heterogeneous reconfigurable architectures, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005., pp.43-50, 2005.
DOI : 10.1109/FPT.2005.1568523

A. Eiche, D. Chillet, S. Pillement, and O. Sentieys, Task placement for dynamic and partial reconfigurable architecture, 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP), pp.228-234
DOI : 10.1109/DASIP.2010.5706269

URL : https://hal.archives-ouvertes.fr/inria-00536714

C. Huriaux, O. Sentieys, and R. Tessier, FPGA architecture support for heterogeneous, relocatable partial bitstreams, 2014 24th International Conference on Field Programmable Logic and Applications (FPL), 2014.
DOI : 10.1109/FPL.2014.6927494

URL : https://hal.archives-ouvertes.fr/hal-01017184

B. Premalatha and S. Umamaheswari, Survey of online hardware task scheduling and placement algorithms for partially reconfigurable computing systems

W. Ye, R. Ernst, T. Benner, and J. Henkel, Fast timing analysis for hardwaresoftware co-synthesis, Computer Design: VLSI in Computers and Processors, 1993. ICCD'93. Proceedings., 1993 IEEE International Conference on, pp.452-457, 1993.

K. Rajesh, G. D. Gupta, and . Micheli, Hardware-software cosynthesis for digital systems, Design & Test of Computers IEEE, vol.10, issue.3, pp.29-41, 1993.

P. Liu, J. Wu, and Y. Wang, Hybrid algorithms for hardware/software partitioning and scheduling on reconfigurable devices, Mathematical and Computer Modelling, vol.58, issue.1-2, pp.409-420, 2013.
DOI : 10.1016/j.mcm.2012.11.001

A. Al-wattar, S. Areibi, and F. Saffih, Efficient On-line Hardware/Software Task Scheduling for Dynamic Run-time Reconfigurable Systems, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum, pp.401-406, 2012.
DOI : 10.1109/IPDPSW.2012.50

H. Kalte and M. Porrmann, Context saving and restoring for multitasking in reconfigurable systems, International Conference on Field Programmable Logic and Applications, 2005., pp.223-228, 2005.
DOI : 10.1109/FPL.2005.1515726

L. Shang, P. Robert, . Dick, K. Niraj, and . Jha, Slopes: hardware?software cosynthesis of low-power real-time distributed embedded systems with dynamically reconfigurable fpgas. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.26, issue.3, pp.508-526, 2007.

J. Teich, Hardware/Software Codesign: The Past, the Present, and Predicting the Future, Proceedings of the IEEE, vol.100, issue.Special Centennial Issue, pp.1411-1430, 2012.
DOI : 10.1109/JPROC.2011.2182009

S. Tarzia, A survey of 3d circuit integration, 2008.

R. Weerasekera, L. Zheng, D. Pamunuwa, and H. Tenhunen, Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs, 2007 IEEE/ACM International Conference on Computer-Aided Design, pp.212-219, 2007.
DOI : 10.1109/ICCAD.2007.4397268

I. Loi, F. Angiolini, and L. Benini, Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow, Proceedings of the Second International Conference on Nano-Networks, 2007.
DOI : 10.4108/ICST.NANONET2007.2033

S. Pasricha, Exploring serial vertical interconnects for 3D ICs, Proceedings of the 46th Annual Design Automation Conference on ZZZ, DAC '09, pp.581-586, 2009.
DOI : 10.1145/1629911.1630061

M. Sadaka, I. Radu, L. Di, and C. , 3D integration: Advantages, enabling technologies & applications, 2010 IEEE International Conference on Integrated Circuit Design and Technology, pp.106-109, 2010.
DOI : 10.1109/ICICDT.2010.5510283

P. Ramm, A. Klumpp, J. Weber, N. Lietaer, M. Taklo et al., 3D Integration technology: Status and application development, 2010 Proceedings of ESSCIRC, pp.9-16
DOI : 10.1109/ESSCIRC.2010.5619857

K. Saban, Xilinx stacked silicon interconnect technology delivers breakthrough fpga capacity, bandwidth, and xilinx stacked silicon interconnect technology delivers breakthrough fpga capacity, bandwidth, and xilinx stacked silicon interconnect technology delivers breakthrough fpga capacity

A. Sheibanyrad, F. Petrot, and A. Jantsch, 3D integration for NoCbased SoC Architectures, 2011.
URL : https://hal.archives-ouvertes.fr/hal-00564660

B. Goplen and S. Sapatnekar, Thermal via placement in 3D ICs, Proceedings of the 2005 international symposium on physical design , ISPD '05, pp.167-174, 2005.
DOI : 10.1145/1055137.1055171

X. Zhou, J. Yang, Y. Xu, Y. Zhang, and J. Zhao, Thermal-aware task scheduling for 3d multicore processors. Parallel and Distributed Systems, IEEE Transactions on, vol.21, issue.1, pp.60-71, 2010.
DOI : 10.1109/tpds.2009.27

J. Li, M. Qiu, J. Niu, T. Laurence, Y. Yang et al., Thermal-aware task scheduling in 3D chip multiprocessor with real-time constrained workloads, ACM Transactions on Embedded Computing Systems, vol.12, issue.2, p.24, 2013.
DOI : 10.1145/2423636.2423642

C. Lung, Y. Ho, D. Kwai, and S. Chang, Thermalaware on-line task allocation for 3d multi-core processor throughput optimization, Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.1-6, 2011.

M. Cox, A. Kumar-singh, A. Kumar, and H. Corporaal, Thermal-aware mapping of streaming applications on 3D Multi-Processor Systems, The 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, pp.11-20, 2013.
DOI : 10.1109/ESTIMedia.2013.6704498

J. A. Valero, J. Septién, D. Mozos, and H. Mecha, 3D FPGA resource management and fragmentation metric for hardware multitasking, 2009 IEEE International Symposium on Parallel & Distributed Processing, pp.1-7, 2009.
DOI : 10.1109/IPDPS.2009.5161201

T. Marconi and T. Mitra, A novel online hardware task scheduling and placement algorithm for 3D partially reconfigurable FPGAs, 2011 International Conference on Field-Programmable Technology, pp.1-6, 2011.
DOI : 10.1109/FPT.2011.6132700

T. Marconi, Online scheduling and placement of hardware tasks with multiple variants on dynamically reconfigurable field-programmable gate arrays, Computers & Electrical Engineering, vol.40, issue.4, pp.1215-1237, 2014.
DOI : 10.1016/j.compeleceng.2013.07.004

D. Aoun, A. Déplanche, and Y. Trinquet, Pfair scheduling improvement to reduce interprocessor migrations, 16th International Conference on Real-Time and Network Systems, 2008.
URL : https://hal.archives-ouvertes.fr/inria-00336513

H. James, A. Anderson, and . Srinivasan, Early-release fair scheduling, Real- Time Systems 12th Euromicro Conference on, pp.35-43, 2000.

C. Bobda and A. Ahmadinia, Dynamic interconnection of reconfigurable modules on reconfigurable devices Design & Test of Computers, IEEE, vol.22, issue.5, pp.443-451, 2005.

J. Jylänki, A thousand ways to pack the bin-a practical approach to twodimensional rectangle bin packing. retrived from http, 2010.

F. Lemonnier, P. Millet, . Gabriel-marchesan-almeida, J. Hubner, S. Becker et al., Kees Goossens, et al. Towards future adaptive multiprocessor systems-on-chip: an innovative approach for flexible architectures, Embedded Computer Systems (SAMOS), 2012 International Conference on, pp.228-235, 2012.

C. Claus, W. Altenried, and . Stechele, Dynamic partial reconfiguration of xilinx fpgas lets systems adapt on the fly, Xcell journal, pp.18-23, 2010.

S. Hauck, Configuration prefetch for single context reconfigurable coprocessors, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays , FPGA '98, pp.65-74, 1998.
DOI : 10.1145/275107.275121

Z. Li and S. Hauck, Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays , FPGA '02, pp.187-195, 2002.
DOI : 10.1145/503048.503076