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. , WCETs (average µ / standard deviation ?) without cache reuse and weighted average WCET reduction, Tasks

. , Comparison of CILP and CLS (schedule length and run time of schedule generation)

. , Cost of estimating cache reuse

, Notations used in the ILP formulation in the adapted stage, p.61

. , The size of code and communicated data for each benchmark (average µ and standard deviation ?)

. , 71 4.4 Performance comparison between ACILP and the double fixed-points algorithm proposed in [94]

. .. , 8 1.2 Task graph of a parallel version of a 8-input Fast Fourier Transform (FFT) application [11], List of Figures 1.1 The influence of scheduling strategies on the WCET of tasks

. , Typical parameters of real-time tasks

. , The variation of execution times of a task depending on the input data or different behavior of environment

. , An example of multi-core architecture

. , The location of cache

. , An example of memory hierarchy

. , Fast Fourier Transform (FFT) application [11]

. , An example of the swapping of tasks' allocation

C. .. Illustrative-example-for,

. , Gain of CILP as compared to NCILP (gain = sl N CILP ? sl CILP sl N CILP * 100) on a 16 cores system

. , Gain of CLS as compared to NCLS (gain = sl N CLS ? sl CLS sl N CLS * 100) on a 16 cores system

. , The reuse pattern found in the Lattice benchmark

N. .. , 43 3.10 Impact of the number of cores on schedule length (CLS method), p.44

C. .. Cls_tl, , p.45

, Comparison of schedules lengths for CLS using different tasks weight functions in the case that tasks are sorted in the list according their top levels, p.46

, Comparison of schedules lengths for CLS using different tasks weight functions in the case that tasks are sorted in the list according their bottom levels, p.47

. , SMEM interleaved address mapping

. , SMEM memory request flow

. , Structure of our proposed time-driven scheduler

. , Illustrative example of the delay to the start time of a task caused by the execution of the sched function

. .. , Illustrative example of the effect of data miss-alignment, p.57

. , Two stages in producing static time-driven cache-conscious schedules to be implemented on a Kalray MPPA-256 compute cluster

. , The difference in the execution of a task in a basic cache-conscious schedule and an adapted cache-conscious schedule

. , 59 4.10 The illustrative example of assigning the trigger time of tasks, p.62

. , The mapping and the schedule of all tasks on two cores of the application whose DAG was depicted in Figure 4.9

, The schedule graph constructed based on the scheduling information in the adapted cache-conscious schedule as depicted in Figure 4.11, p.72

. , The fraction of the overall overhead by each practical issue to the length of schedule graphs