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Architectural Exploration of Network Interface for Energy Efficient 3D Optical Network-on-Chip

Van-Dung Pham 1
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
IRISA-D3 - ARCHITECTURE, Inria Rennes – Bretagne Atlantique
Abstract : In recent years, Optical Networks on Chip (ONoC) became an attractive solution to overcome the limitations of current electrical interconnects, thanks to their low power consumption, low latency, and high data bandwidth properties. However, the optical devices used to build ONoCs suffer from some imperfections which introduce losses during communications. Furthermore, Wavelength Division Multiplexing (WDM) technology can further help to improve ONoC’s bandwidth and latency. However, using WDM introduces new losses and crosstalk noises which negatively impact the Signal to Noise Ratio and therefore reduces energy efficiency of optical interconnects. To address these issues, we first provide a model of optical loss and crosstalk in WDM-based ONoC. We then propose a methodology to reduce the power consumption of optical interconnects relying on forward error correction (FEC). We present two case studies of lightweight FEC with low complexity and high error-correction and implement them on a 28nm FDSOI technology. Finally, we propose the complete design of the optical network interface (ONI) composed of allocation and FEC controller, serial to parallel converters, and laser power driver, which creates a runtime allocation management according to application performance and energy requirements.
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Submitted on : Saturday, December 15, 2018 - 8:56:45 AM
Last modification on : Thursday, November 4, 2021 - 10:54:02 AM
Long-term archiving on: : Saturday, March 16, 2019 - 12:53:11 PM


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  • HAL Id : tel-01956229, version 1


Van-Dung Pham. Architectural Exploration of Network Interface for Energy Efficient 3D Optical Network-on-Chip. Embedded Systems. Université de rennes 1, 2018. English. ⟨tel-01956229⟩



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