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Détail de la phase d'exécution avec ses quatre unités fonctionnelles parallèles ,
,
, Three instruction bundles scheduled by the compiler for the computation of Eq. 1.1
, Per cycle AVF for VEX processor when executing a matrix multiplication, p.24
Error occurrences per storage structure for the matrix multiplication (Normalized) ,
Scheduling running example on an 4-issue VLIW ,
Original VLIW datapath (blue) enhanced with the proposed fault tolerant mechanism (yellow) ,
Voting switch ,
Dep arrays of illustration example from Fig. 4.1b at time t i, p.41 ,
Information extraction unit and Dependency analyzer, p.43 ,
Pre-processing of IDs to occupation arrays ,
Area coverage of each of our technique ,
Scaling of the proposed approach ,
Per cycle AVF for VEX processor ,
Error occurrences per storage structure for the matrix multiplication (Normalized), p.61 ,
Hardware components inserted in the VLIW pipeline ,
Simulation tool flow for performance evaluation results, p.68 ,
, 5 permanent errors, p.69
VLIW enhanced with the proposed mechanism ,
Illustration example of the proposed mechanism ,
Components of complex FU enhanced with BICS ,
79 5.10 Proposed mechanism performance for fft benchmark under different number of faults and fault duration ,
Area footprint and power estimation results ,
Area and power overhead to the unprotected approach ,
63 5.1 DMR (TMR) performance overhead (%) for the proposed approach with respect to DMR (TMR) without faults ,
Performance gain (%) estimation of the proposed approach over existing approaches for multiple permanent errors ,
Performance comparison (execution cycles) under several multiple faults and average performance overhead (%) ,
Step) for each group ,
, , vol.84, p.105
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,
, ILP Instruction Level Parallelism
, IM Instruction Memory
, IRB Instruction Replication and Binding
, ISA Instruction-Set Architecture
, ISS Instruction Set Simulator
, NBTI Negative-Bias Temperature Instability. NOP No OPeration instructions
,
, PSF Processors State Failure
, PVT Process, Voltage, and Temperature
, TLP Thread Level Parallelism
, VLIW Very Long Instruction Word. WAR Write After Read