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Architectural and Protocol Exploration for 3D Optical Network-on-Chip

Jiating Luo 1
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : Evolution of Multi-Processor System-on-Chip (MPSoC) is moving towards the integra- tion of hundreds of cores on a single chip. Designing an efficient interconnect for such complex architectures is challenging due to the ever growing data exchange between processors. In this context, silicon photonics is proposed as an emerging technology for future generation on-chip interconnects, providing several prospective advantages such as low transmission latency and high bandwidth. Optical Network-on-Chip (ONoC) are based on waveguides, carrying optical signals, and optical devices allowing to inject or drop the signals into this waveguide from an electrical interface. The waveguide can support multiple communications at the same time on different wavelengths by using Wavelength Division Multiplexing (WDM), providing a significant increase in bandwidth. However, simultaneous transmissions, on close adjacent wavelengths, may introduce inter-channel crosstalk noise through different optical switching elements within the network, which results in high Bit Error Ratio (BER). Besides, the higher the number of signals propagating simultaneously, the higher the crosstalk and the higher the laser output power needs. This leads to the following conflicting objectives: high-performance tends to rely on an exhaustive use of the wavelength while low-power communication prefers low bandwidth channel. Using an ONoC to execute a given application is thus a tedious task, especially if performance, power and BER objectives are likely to evolve with the execution context. In this thesis, we assess communication performance and energy efficiency of ONoC from offline and online wavelength allocation respectively. Firstly, we propose an offline methodology which combines wavelength allocation and laser power scaling to find the best performance and energy consumption trade-off for ONoC-based MPSoC. The methodology is formed as a framework handling several inputs, such as architecture, application, mapping, and device parameters. It allows not only the exploration of design space at both device level and system level, but also the generation of per- formance and energy efficiency trade-off based on a set of defined input parameters. The resulting Pareto solutions include low-power solutions, which tend to minimize the number of used wavelengths, and high-performance solutions, for which multiple wavelengths are allocated to shorten the communication time. As an example, for a 63-task application running on 64 cores, the relative variation in the execution time and energy is 60% and 39% respectively. Finally, these solutions can be embedded in the controller and deployed at run-time according to execution requirement (e.g. high performance and low power). Secondly, in order to handle a dynamic workload and run- time deployment of tasks, dynamic policies to allocate the optical resources at run-time in a MPSoC architectures should be considered. We start by proposing a Tree-based electrical set-up control network, named TbNoC, that centrally handle the request to reduce channel allocation set-up latency. A minimization of crosstalk algorithm, which allocates distinct and separate wavelengths for optical signals, is employed to reduce the crosstalk, hence, the energy efficiency is improved. In summarize, how to allocate efficiently wavelengths to improve energy efficiency and performance in ONoC are extensively discussed and handled in this thesis.
Keywords : Network on chip NoC
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Submitted on : Thursday, January 3, 2019 - 10:50:38 AM
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  • HAL Id : tel-01956255, version 1


Jiating Luo. Architectural and Protocol Exploration for 3D Optical Network-on-Chip. Hardware Architecture [cs.AR]. Université de Rennes 1 [UR1], 2018. English. ⟨tel-01956255⟩



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