M. Seif, E. Farjallah, F. Badets, E. Chabchoub, C. Layer et al., Improvement of the tolerated raw bit error rate in NAND Flash-based SSDs with the help of embedded statistics, 2017 IEEE International Test Conference (ITC), pp.1-9, 2017.
URL : https://hal.archives-ouvertes.fr/lirmm-01582185

-. E. Farjallah, J. Armani, L. Dilillo, V. Gherman, ;. E. Farjallah et al., Improvement of the tolerated raw bit error rate in NAND Flash-based SSDs with selective refresh, 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), (Taormina), pp.1-5, 2018.
URL : https://hal.archives-ouvertes.fr/lirmm-02008002

P. K. Lala, Self-Checking and Fault Tolerance Digital Design, 2001.

N. H. Weste and D. M. Harris, CMOS VLSI design: a circuits and systems perspective, 2011.

R. Micheloni, L. Crippa, and A. Marelli, Inside NAND Flash Memories, 2010.

;. Swissbit and &. Germany, X-500 / X-55 Series SLC vs, 2014.

I. and M. Technology, Nand flash 101: An introduction to nand flash and how to design it in to your next product, 2006.

F. James, T. Salzman, and . Instruments, Total Ionizing Dose (TID) and Single Event Effects (SEE) Test Report, 2013.

W. Paper, A. R. Olson, and D. J. Langlois, Solid State Drives Data Reliability and Lifetime -Imation Corp, 2008.

A. Spinelli, C. Compagnoni, and A. Lacaita, Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3d Devices, Computers, vol.6, issue.2, p.16, 2017.

X. Wang, G. Dong, L. Pan, and R. Zhou, Error Correction Codes and Signal Processing in Flash Memory, Flash Memories, pp.57-82
DOI : 10.5772/19083
URL : https://www.intechopen.com/chapter/pdf-download/19378

Y. Cai, O. Mutlu, E. F. Haratsch, and K. Mai, Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation, IEEE, pp.123-130, 2013.
DOI : 10.1109/iccd.2013.6657034

R. Baumann, Radiation-induced soft errors in advanced semiconductor technologies, IEEE Transactions on Device and Materials Reliability, vol.5, issue.3, pp.305-316, 2005.
DOI : 10.1109/tdmr.2005.853449

T. Calin, M. Nicolaidis, and R. Velazco, Upset hardened memory design for submicron CMOS technology, IEEE Transactions on Nuclear Science, 1996.
DOI : 10.1109/23.556880
URL : https://hal.archives-ouvertes.fr/hal-01412461

Y. Cai, G. Yalcin, O. Mutlu, and E. F. Haratsch, Error Analysis and Retention-Aware Error Management for NAND Flash Memory, vol.17, p.25, 2013.

N. Mielke, T. Marquart, N. Wu, J. Kessenich, H. Belgal et al., Bit error rate in NAND Flash memories, IEEE, pp.9-19, 2008.

E. Dupont, M. Nicolaidis, and P. Rohr, Embedded robustness ips for transient-error-free ics, IEEE Design Test of Computers, vol.19, issue.3, pp.54-68, 2002.
URL : https://hal.archives-ouvertes.fr/hal-00013743

D. Kearns and . Cypress, Practical Guide to Endurance and Data Retention, 2017.

I. , International technology roadmap for semiconductor -process integration devices and structures, Tech. Rep, 2013.

C. T. , Failure mechanism based stress test qualification for integrated circuits, 2007.

R. A. Normann, First high-temperature electronics products survey, Sandia National Laboratories, Tech. Rep, 2005.

A. Muffler and X. , Challenges for Non Volatile Memory (NVM) for Automotive High Temperature Operating Conditions, 2017.

R. Cojbasic and Y. Leblebici, Design of high-temperature SRAM for reliable operation beyond 250 ? C, 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp.2545-2548, 2015.

R. Cojbasic, O. Cogal, P. Meinerzhagen, C. Senning, C. Slater et al., FireBird: PowerPC e200 based SoC for high temperature operation, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, pp.1-4, 2013.

S. M. Sze and K. K. Ng, Physics of semiconductor devices, 2007.

D. Wolpert and P. Ampadu, Temperature effects in semiconductors, Managing Temperature Effects in Nanoscale Adaptive Systems, pp.15-33, 2012.

P. G. Neudeck, R. S. Okojie, and L. Chen, High-temperature electronics-a role for wide bandgap semiconductors?, Proceedings of the IEEE, vol.90, issue.6, pp.1065-1076, 2002.

C. Park, J. P. John, K. Klein, J. Teplik, J. Caravella et al., Reversal of temperature dependence of integrated circuits operating at very low voltages, Electron Devices Meeting, pp.71-74, 1995.

F. Fallah, Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits, IEICE Transactions on Electronics, issue.4, pp.509-519, 2005.

J. Black, Electromigration -a brief survey and some recent results, IEEE Transactions on Electron Devices, vol.16, issue.4, pp.338-347, 1969.

I. Englander, The architecture of computer hardware, system software, and networking: an information technology approach, 2009.

, ITRS 2.0 Home Page

J. Meena, S. Sze, U. Chand, and T. Tseng, Overview of emerging nonvolatile memory technologies, Nanoscale Research Letters, vol.9, 2014.

Y. Developpement, Emerging Non Volatile Memory Technology and Market Report, 2015.

P. Cappelletti, C. Golla, P. Olivo, E. Zanoni, and F. Memories, , 1999.

R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, Introduction to flash memory, Proceedings of the IEEE, vol.91, pp.489-502, 2003.

H. Li, Modeling of Threshold Voltage Distribution in NAND Flash Memory: A Monte Carlo Method, IEEE Transactions on Electron Devices, vol.63, issue.9, pp.3527-3532, 2016.

A. Kent and J. G. Williams, Encyclopedia of microcomputers, vol.9, 1992.

T. Heijmen, P. Roche, G. Gasiot, and K. Forbes, A Comparative Study on the Soft-Error Rate of Flip-Flops from 90-nm Production Libraries, pp.204-211, 2006.

A. S. Sedra and K. C. Smith, Microelectronic circuits, 5th ed., ser. The Oxford series in electrical and computer engineering, 2004.

G. Apostolidis, D. Balobas, and N. Konofaos, Design and simulation of 6t SRAM cell architectures in 32nm technology, Journal of Engineering Science and Technology Review, vol.9, issue.5, pp.145-149, 2016.

G. Tsiligiannis, I. E. Vatajelu, L. Dilillo, A. Bosio, S. Pravossoudovitch et al., SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations, On-Line Testing Symposium (IOLTS), pp.145-150, 2013.
URL : https://hal.archives-ouvertes.fr/lirmm-00818955

E. Vatajelu, G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard et al., On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
URL : https://hal.archives-ouvertes.fr/lirmm-01238413

N. Edri, S. Fraiman, A. Teman, and A. Fish, Data retention voltage detection for minimizing the standby power of SRAM arrays, IEEE, pp.1-5, 2012.

H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J. Rabaey, SRAM leakage suppression by minimizing standby supply voltage, pp.55-60, 2004.

S. Tavernier, Experimental Techniques in Nuclear and Particle Physics, 2010.

J. Autran, S. Semikh, D. Munteanu, S. Serre, G. Gasiot et al., Soft-Error Rate of Advanced SRAM Memories: Modeling and Monte Carlo Simulation, Numerical Simulation -From Theory to Industry, M. Andriychuk, 2012.
URL : https://hal.archives-ouvertes.fr/hal-02120900

. Microsemi, Neutron-induced single event upsets (SEU) FAQ, 2011.

R. Antoni and L. Bourgois, Quantities and Fundamental Units of External Dosimetry, Applied Physics of External Radiation Exposure, pp.1-42, 2017.

O. U. Press, Icru report 85, Journal of the International Commission on Radiation Units and Measurements, vol.11, issue.1, 2011.

E. Petersen, Single Event Effects in Aerospace, 2011.

D. J. Dimaria and E. Cartier, Mechanism for stressâ??induced leakage currents in thin silicon dioxide films, Journal of Applied Physics, vol.78, issue.6, pp.3883-3894, 1995.

E. Rosenbaum, Mechanism of Stress-Induced Leakage Current in MOS Capacitors, IEEE TRANSACTIONS ON ELECTRON DEVICES, vol.44, issue.2, p.7, 1997.

D. Sheldon and M. Freie, National Aeronautics and Space Administration

J. Heidecker, NAND Flash Screening and Qualification Guideline for Space Application, National Aeronautics and Space Administration, pp.12-13

D. Bertozzi, S. D. Carlo, S. Galfano, M. Indaco, P. Olivo et al., Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers, ACM Transactions on Embedded Computing Systems, vol.14, issue.1, pp.1-24, 2015.

S. D. Carlo, S. Galfano, M. Indaco, P. Prinetto, D. Bertozzi et al., FLARES: An Aging Aware Algorithm to Autonomously Adapt the Error Correction Capability in NAND Flash Memories, ACM Transactions on Architecture and Code Optimization, vol.11, issue.3, pp.1-25, 2014.

Y. Cai, E. F. Haratsch, O. Mutlu, and K. Mai, Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis and Modeling, pp.1285-1290, 2013.

Y. Cai, Y. Luo, E. F. Haratsch, K. Mai, and O. Mutlu, Data retention in MLC NAND flash memory: Characterization, optimization, and recovery, IEEE, pp.551-563, 2015.

Y. Cai, G. Yalcin, O. Mutlu, E. F. Haratsch, A. Cristal et al., Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime, IEEE, pp.94-101, 2012.

P. E. Dodd, M. R. Shaneyfelt, J. R. Schwank, and J. A. Felix, Current and Future Challenges in Radiation Effects on CMOS Electronics, IEEE Transactions on Nuclear Science, vol.57, issue.4, pp.1747-1763, 2010.

L. H. Mutuel, Aviation Research Division, Atlantic City International Airport, Final report DOT/FAA/TC-15/62, William J. Hughes Technical Center, 2016.

C. Slayman, Soft error trends and mitigation techniques in memory devices, 2011 Proceedings -Annual Reliability and Maintainability Symposium, pp.1-5, 2011.

F. Yu, J. Liu, Z. Huang, H. Luo, and Z. Lu, Overview of radiation hardening techniques for ic design, Information Technology Journal, vol.9, issue.6, pp.1068-1080, 2010.

M. Haghi and J. Draper, The 90 nm Double-DICE storage element to reduce Single-Event upsets, Circuits and Systems, 2009. MWSCAS'09. 52nd IEEE International Midwest Symposium on, pp.463-466, 2009.

L. Chang, Hybrid solid-state disks: Combining heterogeneous nand flash in large ssds, 2008 Asia and South Pacific Design Automation Conference, pp.428-433, 2008.

Y. Chen, Flash Memory Reliability NEPP 2008 Task Final Report, 2008.

. Jedec, . State, and . Association, JEDEC PUBLICATION: Failure Mechanisms and Models for Semiconductor Devices, 2009.

, JEDEC STANDARD: Solid-State Drive (SSD) Requirements and Endurance Test Method, 2016.

V. Mohan, S. Sankar, S. Gurumurthi, and W. Redmond, reFresh SSDs: Enabling high endurance, low cost flash in datacenters, Univ. of Virginia, 2012.

. Micron-technology and . Inc, Uprating Semiconductors for High-Temperature Applications, 2004.

P. Ellerman, Calculating Reliability using FIT & MTTF: Arrhenius HTOL Model, 2012.

K. Lee, M. Kang, S. Seo, D. H. Li, J. Kim et al., Analysis of Failure Mechanisms and Extraction of Activation Energies Ea in 21-nm nand Flash Cells, IEEE Electron Device Letters, vol.34, issue.1, pp.48-50, 2013.

K. Lee, M. Kang, S. Seo, D. Kang, S. Kim et al., Activation Energies Ea of Failure Mechanisms in Advanced NAND Flash Cells for Different Generations and Cycling, IEEE Transactions on Electron Devices, vol.60, issue.3, pp.1099-1107, 2013.

N. Sundby and D. Taylor, Beyond Capacity: Storage Architecture Choices for the Modern Datacenter, 2014.

K. Kingston, The Difference Between Enterprise & Client SSD

J. Meza, Q. Wu, S. Kumar, and O. Mutlu, A Large-Scale Study of Flash Memory Failures in the Field, Proceedings of the 2015 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems -SIGMETRICS '15, pp.177-190, 2015.

Y. Cai, S. Ghose, E. F. Haratsch, Y. Luo, and O. Mutlu, Errors in flash-memory-based solid-state drives: Analysis, mitigation, and recovery, CoRR, 2017.
DOI : 10.1007/978-981-13-0599-3_9

R. Hotwire and . Reliability-e-magazine, Chi-Squared Distribution and Reliability Demonstration Test Design, vol.116, 2010.

P. Ellerman and M. Corp, Calculating Chi-squared for Reliability Equations, 2012.

N. Kr and . Shukla, Analysis of the Effect of Temperature Variations on Sub-threshold Leakage Current in P3 and P4 SRAM Cells at Deep Sub-micron CMOS Technology, International Journal of Computer Applications, vol.35, issue.5, pp.8-13, 2011.

H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J. Rabaey, SRAM leakage suppression by minimizing standby supply voltage, SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720), pp.55-60, 2004.

N. Edri, S. Fraiman, A. Teman, and A. Fish, Data retention voltage detection for minimizing the standby power of SRAM arrays, 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, pp.1-5, 2012.

G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch et al., Temperature Impact on the Neutron SER of a Commercial 90nm SRAM, NSREC: Nuclear and Space Radiation Effects Conference, pp.1-4, 2013.
URL : https://hal.archives-ouvertes.fr/lirmm-00805291

G. Tsiligiannis, E. I. Vatajelu, L. Dilillo, A. Bosio, P. Girard et al., Sram soft error rate evaluation under atmospheric neutron radiation and pvt variations, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), pp.145-150, 2013.
DOI : 10.1109/iolts.2013.6604066
URL : https://hal.archives-ouvertes.fr/lirmm-00818955

M. Bagatin, S. Gerardin, A. Paccagnella, C. Andreani, G. Gorini et al., Temperature dependence of neutron-induced soft errors in SRAMs, Microelectronics Reliability, vol.52, issue.1, pp.289-293, 2012.

D. Truyen, J. Boch, B. Sagnes, N. Renaud, E. Leduc et al., Temperature Effect on Heavy-Ion Induced Parasitic Current on SRAM by Device Simulation: Effect on SEU Sensitivity, IEEE Transactions on Nuclear Science, vol.54, issue.4, pp.1025-1029, 2007.
URL : https://hal.archives-ouvertes.fr/hal-00327115

R. Naseer, Y. Boulghassoul, J. Draper, S. Dasgupta, and A. Witulski, Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM, 2007 IEEE International Symposium on Circuits and Systems, pp.1879-1882, 2007.
DOI : 10.1109/iscas.2007.378282
URL : http://www.isi.edu/~draper/papers/iscas07_naseer.pdf

T. Liu, C. Geng, Z. Zhang, F. Zhao, S. Gu et al., Impact of temperature on single event upset measurement by heavy ions in SRAM devices, Journal of Semiconductors, vol.35, issue.8, 2014.

G. R. Srinivasan, P. C. Murley, and H. K. Tang, Accurate, predictive modeling of soft error rate due to cosmic rays and chip alpha radiation, Proceedings of 1994 IEEE International Reliability Physics Symposium, pp.12-16, 1994.

B. Gill, M. Nicolaidis, F. Wolff, C. Papachristou, and S. Garverick, An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories, Design, Automation and Test in Europe, pp.592-597, 2005.
URL : https://hal.archives-ouvertes.fr/hal-00013724

F. Wrobel, L. Dilillo, A. D. Touboul, V. Pouget, and F. Saigne, Determining Realistic Parameters for the Double Exponential Law that Models Transient Current Pulses, IEEE Transactions on Nuclear Science, vol.61, issue.4, pp.1813-1818, 2014.
DOI : 10.1109/tns.2014.2299762
URL : https://hal.archives-ouvertes.fr/lirmm-01234429

F. Wrobel, L. Dilillo, A. D. Touboul, and F. Saigne, Comparison of the transient current shapes obtained with the diffusion model and the double exponential law -Impact on the SER, 2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS), pp.1-4, 2013.
URL : https://hal.archives-ouvertes.fr/lirmm-01237599

G. Torrens, FPGA SRAM Soft Error Radiation Hardening, Field -Programmable Gate Array, G. Dekoulis, 2017.
DOI : 10.5772/66195
URL : https://www.intechopen.com/citation-pdf-url/53004

A. Maru, H. Shindou, T. Ebihara, A. Makihara, T. Hirao et al., DICE-Based Flip-Flop With SET Pulse Discriminator on a 90 nm Bulk CMOS Process, IEEE Transactions on Nuclear Science, 2010.

E. Seevinck, F. J. List, and J. Lohstroh, Static-noise margin analysis of MOS SRAM cells, IEEE Journal of solid-state circuits, vol.22, issue.5, pp.748-754, 1987.

, Predictive Technology Model (PTM)

Y. Cao, Predictive Technology Model of Conventional CMOS Devices, Predictive Technology Model for Robust Nanoelectronic Design, pp.7-23, 2011.