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Conference Papers Year : 2013

Verification-guided Voter Minimization in Triple-Modular Redundant Circuits

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Programming Languages [cs.PL] Performance [cs.PF]

Pascal Fradet  : Connect in order to contact the contributor

https://inria.hal.science/hal-00911768

Submitted on : Friday, November 29, 2013-6:44:08 PM

Last modification on : Thursday, April 4, 2024-9:06:50 PM

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hal-00911768 , version 1 (29-11-2013)

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  • HAL Id : hal-00911768 , version 1

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Dmitry Burlyaev, Pascal Fradet, Alain Girault. Verification-guided Voter Minimization in Triple-Modular Redundant Circuits. Design, Automation and Test in Europe Conference, DATE'14, Mar 2014, Dresden, Germany. ⟨hal-00911768⟩

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UNIV-RENNES1 UGA CNRS INRIA IRISA LIG INRIA2 LIG-MFML-SPADES UR1-MATH-STIC UR1-UFR-ISTIC UNIV-RENNES UR1-MATH-NUM LIG_SIDCH
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