inria-00424016, version 2

## Fast architectures for the $\eta_T$ pairing over small-characteristic supersingular elliptic curves

Jean-Luc Beuchat () a1, Jérémie Detrey () b2, Nicolas Estibals () c2, Eiji Okamoto () a1, Francisco Rodríguez-Henríquez () d3

IEEE Transactions on Computers 60, 2 (2011) 266-281

Résumé : This paper is devoted to the design of fast parallel accelerators for the cryptographic $\eta_T$ pairing on supersingular elliptic curves over finite fields of characteristics two and three. We propose here a novel hardware implementation of Miller's algorithm based on a parallel pipelined Karatsuba multiplier. After a short description of the strategies we considered to design our multiplier, we point out the intrinsic parallelism of Miller's loop and outline the architecture of coprocessors for the $\eta_T$ pairing over $\F_{2^m}$ and $\F_{3^m}$. Thanks to a careful choice of algorithms for the tower field arithmetic associated with the $\eta_T$ pairing, we manage to keep the pipelined multiplier at the heart of each coprocessor busy. A final exponentiation is still required to obtain a unique value, which is desirable in most cryptographic protocols. We supplement our pairing accelerators with a coprocessor responsible for this task. An improved exponentiation algorithm allows us to save hardware resources. According to our place-and-route results on Xilinx FPGAs, our designs improve both the computation time and the area-time trade-off compared to previously published coprocessors.

• Domaine : Informatique/Cryptographie et sécurité
Informatique/Arithmétique des ordinateurs
Informatique/Architecture
• Versions disponibles :  v1 (16-10-2009) v2 (29-11-2010)

• inria-00424016, version 2
• oai:hal.inria.fr:inria-00424016
• Contributeur :
• Soumis le : Jeudi 25 Novembre 2010, 15:05:28
• Dernière modification le : Mercredi 9 Février 2011, 17:03:06