Graph Constraints in Embedded System Design
Abstract
In this paper, we present application of graph constraints combined with finite domain constraints for embedded system optimization problems. In particular, we present methods for identification and selection of computational patterns as well as application scheduling with these patterns that has direct application in ASIP processor design. In this work we use connected component, (sub)graph isomorphism and clique constraints. Our experimental results show that these methods work for relatively large examples and provide much better results than previous heuristic based approaches.