Automatic generation of polynomial-based hardware architectures for function evaluation

Florent De Dinechin 1, 2 Mioara Joldes 1, 2 Bogdan Pasca 1, 2
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : Many applications require the evaluation of some function through polynomial approximation. This article details an architecture generator for this class of problems that improves upon the literature in two aspects. Firstly, it benefits from recent advances related to constrained-coefficient polynomial approximation. Secondly, it refines the error analysis of polynomial evaluation to reduce the size of the multipliers used. As a result, architectures for evaluating arbitrary functions with precisions up to 64 bits, making efficient use of the resources of recent FPGAs, can be obtained in seconds. An open-source implementation is provided in the FloPoCo project.
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Communication dans un congrès
Application-specific Systems, Architectures and Processors, Jul 2010, Rennes, France. IEEE, 2010
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https://hal-ens-lyon.archives-ouvertes.fr/ensl-00470506
Contributeur : Florent De Dinechin <>
Soumis le : mardi 6 avril 2010 - 17:03:10
Dernière modification le : mercredi 1 décembre 2010 - 22:54:00
Document(s) archivé(s) le : vendredi 19 octobre 2012 - 11:20:32

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Florent De Dinechin, Mioara Joldes, Bogdan Pasca. Automatic generation of polynomial-based hardware architectures for function evaluation. Application-specific Systems, Architectures and Processors, Jul 2010, Rennes, France. IEEE, 2010. <ensl-00470506>

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