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Conference Papers Year : 2011

Parallelism Level Impact on Energy Consumption in Reconfigurable Devices

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Abstract

Nowadays, System-on-Chip architectures are composed of several execution resources which support complex applications. As it shares silicon area and limits the cost of the global circuit, the embedding of a reconfigurable resource in these SoC provides flexibility to the hardware. In this case, several implementations of the same algorithm, offering different characteristics, can be considered in order to optimize performances. In general, the tasks mapped on reconfigurable resources are algorithms that can be defined through several levels of parallelism. Clearly, parallelism directly affects the area and the execution time, this paper shows that the energy consumption is not constant, and decreases when the parallelism grows up.
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Dates and versions

hal-00650631 , version 1 (11-12-2011)

Identifiers

  • HAL Id : hal-00650631 , version 1

Cite

Robin Bonamy, Daniel Chillet, Sebastien Bilavarn, Olivier Sentieys. Parallelism Level Impact on Energy Consumption in Reconfigurable Devices. HEART (International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies), Imperial college, Jun 2011, London, United Kingdom. pp.104-105. ⟨hal-00650631⟩
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