Virtual Platform for Embedded System Power Estimation

Abstract : In this paper, we propose a virtual platform for power estimation of processor based embedded systems. Our platform consists of a combination of Functional Level Power Analysis (FLPA) for power modeling and fast system prototyping for transactional simulation. In this proposal, we aim at esti- mating power automatically with the help of power models and SystemC IP libraries. These libraries are enriched with different power models and various hardware components required by the embedded platforms. This will allow to use our proposed virtual platform to port various hardware systems and applications in the same environment in order to satisfy the requirements of reliable and efficient design space exploration. Our experiments performed on this virtual embedded platform show that the obtained power estimation results are less than 3% of error in an average for all the processor when compared to the real board measurements.
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Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Jean-Luc Dekeyser. Virtual Platform for Embedded System Power Estimation. DATE-2012, Rainer Leupers, Mar 2012, Dresden, Germany. ⟨hal-00673911⟩

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