A digital CMOS fully connected neural network with in-circuit learning capability and automatic identification of spurious attractors

Abstract : Describes a completely connected feedback network with 64 binary neurons, using digital CMOS technology. The architecture implements a linear systolic loop, in which each neuron stores locally its own synaptic coefficients, and the potential calculation needs N time steps, each performing N partial weighted sums, to realize the N^2 operations needed. It implements internal learning capabilities, using the Widrow-Hoff rule, which converges towards the pseudo-inverse rule by iteration, thus allowing partial correlation between prototypes, and a higher capacity, compared to the Hebb rule. Also, it implements an internal mechanism for detecting relaxations on spurious states. The average retrieval speed is about 20 mu s, whereas the learning time is approximately 15 to 30 ms for 15 moderately correlated prototypes.
Type de document :
Communication dans un congrès
EURO-ASIC'91: The European Conference on Design Automation with The European Event in ASIC Design, Apr 1991, Paris, France. pp.247 -250, 1991, 〈10.1109/EUASIC.1991.212858〉
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https://hal.inria.fr/hal-00700091
Contributeur : Jean-Dominique Gascuel <>
Soumis le : mardi 22 mai 2012 - 12:21:20
Dernière modification le : jeudi 10 mai 2018 - 02:06:53

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J.-D. Gascuel, M. Weinfeld, S. Chakroun. A digital CMOS fully connected neural network with in-circuit learning capability and automatic identification of spurious attractors. EURO-ASIC'91: The European Conference on Design Automation with The European Event in ASIC Design, Apr 1991, Paris, France. pp.247 -250, 1991, 〈10.1109/EUASIC.1991.212858〉. 〈hal-00700091〉

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