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Efficient custom instruction enumeration for extensible processors

Emmanuel Casseau 1 Chenglong Xiao 1
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
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Conference papers
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https://hal.inria.fr/hal-00746745
Contributor : Emmanuel Casseau <>
Submitted on : Monday, October 29, 2012 - 3:53:31 PM
Last modification on : Friday, March 6, 2020 - 1:20:35 AM

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  • HAL Id : hal-00746745, version 1

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CNRS | INRIA | UNIV-RENNES1 | IRISA | IRISA-D3 | UR1-UFR-ISTIC | UNIV-RENNES | INSTITUT-TELECOM

Citation

Emmanuel Casseau, Chenglong Xiao. Efficient custom instruction enumeration for extensible processors. IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Sep 2011, Santa Monica, United States. pp.211-214. ⟨hal-00746745⟩

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