Beyond CPU Frequency Scaling for a Fine-grained Energy Control of HPC Systems

Ghislain Landry Tsafack Chetsa 1, 2 Laurent Lefevre 2, 3 Jean-Marc Pierson 4 Patricia Stolf 4 Georges Da Costa 4
1 AVALON - Algorithms and Software Architectures for Distributed and HPC Platforms
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
2 ENS Lyon - École normale supérieure - Lyon
3 RESO - Protocols and softwares for very high-performance network
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
4 IRIT - Institut de recherche en informatique de Toulouse
Abstract : Modern high performance computing subsystems (HPC) - including processor, network, memory, and IO - are provided with power management mechanisms. These include dynamic speed scaling and dynamic resource sleeping. Understanding the behavioral patterns of high performance computing systems at runtime can lead to a multitude of optimization opportunities including controlling and limiting their energy usage. In this paper, we present a general purpose methodology for optimizing energy performance of HPC systems consid- ering processor, disk and network. We rely on the concept of execution vector along with a partial phase recognition technique for on-the-fly dynamic management without any a priori knowledge of the workload. We demonstrate the effectiveness of our management policy under two real-life workloads. Experimental results show that our management policy in comparison with baseline unmanaged execution saves up to 24% of energy with less than 4% performance overhead for our real-life workloads.
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Communication dans un congrès
24th International Symposium on Computer Architecture and High Performance Computing, Oct 2012, New York City, United States. 2012
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Dernière modification le : mercredi 23 mai 2018 - 17:58:06
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Ghislain Landry Tsafack Chetsa, Laurent Lefevre, Jean-Marc Pierson, Patricia Stolf, Georges Da Costa. Beyond CPU Frequency Scaling for a Fine-grained Energy Control of HPC Systems. 24th International Symposium on Computer Architecture and High Performance Computing, Oct 2012, New York City, United States. 2012. 〈hal-00752883〉

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