Relating Requirement and Design Variabilities

Jean-Vivien Millo 1 S. Ramesh 2
1 AOSTE - Models and methods of analysis and optimization for systems with real-time and embedding constraints
CRISAM - Inria Sophia Antipolis - Méditerranée , Inria Paris-Rocquencourt, COMRED - COMmunications, Réseaux, systèmes Embarqués et Distribués
Abstract : This paper presents a novel approach to relate the variabilities that exist at the requirement and design levels in a Software Product Line (SPL). This approach is based upon two key observations: (i) it is not only the requirements, but also the design contain variability information, (ii) The variability information at the requirement and design levels are expressed differently and at different levels of abstraction. In the context of an SPL composed of features including variability, the proposed method relates every feature configuration (evaluation of the configuration parameters) at the design level with a feature instantiation at the requirement level. The core step in the method is a conformance checking procedure that is based upon the well-known automata containment algorithm used in formal verification of finite state systems. The method has been implemented on top of the well-known verification tool, SPIN, and then experimented on an industrial example with encouraging results.
Type de document :
Communication dans un congrès
APSEC '12 - Proceedings of the 19th Asia-Pacific Software Engineering Conference 2012, Dec 2012, Hong-Kong, Hong Kong SAR China. pp.35-42, 2012, <10.1109/APSEC.2012.67>
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https://hal.inria.fr/hal-00799094
Contributeur : Team Aoste <>
Soumis le : lundi 11 mars 2013 - 15:20:06
Dernière modification le : lundi 5 octobre 2015 - 17:01:06

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Jean-Vivien Millo, S. Ramesh. Relating Requirement and Design Variabilities. APSEC '12 - Proceedings of the 19th Asia-Pacific Software Engineering Conference 2012, Dec 2012, Hong-Kong, Hong Kong SAR China. pp.35-42, 2012, <10.1109/APSEC.2012.67>. <hal-00799094>

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