Hybrid System Level Power Consumption Estimation for 29FPGA-Based MPSoC

Santhosh Kumar Rethinagiri 1, 2 Rabie Ben Atitallah 1 Smal Niar Eric Senn 3 Jean-Luc Dekeyser 2
2 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, Inria Lille - Nord Europe
3 Lab-STICC_UBS_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
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Conference papers
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https://hal.inria.fr/hal-00842401
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Submitted on : Monday, July 8, 2013 - 3:15:41 PM
Last modification on : Monday, February 25, 2019 - 3:14:11 PM

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Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Smal Niar, Eric Senn, Jean-Luc Dekeyser. Hybrid System Level Power Consumption Estimation for 29FPGA-Based MPSoC. 29th IEEE International Conference on Computer Design ICCD 2011, 2011, Unknown. ⟨hal-00842401⟩

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