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Off-line mapping of real-time applications onto massively parallel processor arrays

Thomas Carle 1 Manel Djemal 1 Dumitru Potop-Butucaru 1 Robert de Simone 1 Zhen Zhang 1
1 AOSTE - Models and methods of analysis and optimization for systems with real-time and embedding constraints
CRISAM - Inria Sophia Antipolis - Méditerranée , Inria Paris-Rocquencourt, Laboratoire I3S - COMRED - COMmunications, Réseaux, systèmes Embarqués et Distribués
Abstract : On-chip networks (NoCs) used in chip-multiprocessors (CMPs) pose significant challenges to both on-line and off-line real-time scheduling approaches. They have large numbers of potential contention points, have limited internal buffering capabilities, and network control operates at the scale of small data packets. Therefore, precise schedulability analysis requires scalable algorithms working on hardware models with a level of detail that is unprecedented in real-time scheduling. We consider here an off-line scheduling approach, and we target massively parallel processor arrays (MPPAs), which are CMPs with large numbers (hundreds) of processing cores. We first identify and compare the hardware mechanisms supporting precise timing analysis and efficient resource allocation in existing MPPA platforms. We determine that the NoC should ideally provide the means of enforcing a global communications schedule that is computed off-line and which is synchronized with the scheduling of computations on processors. On the software side, we propose a novel allocation and scheduling method capable of synthesizing such global computation and communication schedules covering all the execution, communication, and memory resources in an MPPA. To allow an efficient use of the hardware resources, our method takes into account the specificities of MPPA hardware and implements advanced scheduling techniques such as pre-computed preemption of data transmissions and pipelined scheduling. We evaluate our technique by mapping two signal processing applications, for which we obtain good latency, throughput, and resource use figures.
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Submitted on : Monday, December 16, 2013 - 5:00:07 PM
Last modification on : Tuesday, January 11, 2022 - 11:16:21 AM
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  • HAL Id : hal-00919411, version 1



Thomas Carle, Manel Djemal, Dumitru Potop-Butucaru, Robert de Simone, Zhen Zhang. Off-line mapping of real-time applications onto massively parallel processor arrays. [Research Report] RR-8429, INRIA. 2013. ⟨hal-00919411⟩



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