A Lifting-Based Discrete Wavelet Transform and Discrete Wavelet Packet Processor with Support for Higher Order Wavelet Filters

Abstract : The major challenge in the wavelet transforms is that there exist different classes of wavelet filters for different kinds of applications. In this chapter, we propose a generalized lifting-based wavelet processor that can perform various forward and inverse Discrete Wavelet Transforms (DWTs) and Discrete Wavelet Packets (DWPs) that also supports higher order wavelet filters. Our architecture is based on Processing Elements (PEs) which can perform either prediction or update on a continuous data stream in every two clock cycles. We also consider the normalization step which takes place at the end of the forward DWT/DWP or at the beginning of the inverse DWT/DWP. Because different applications require different number of samples for the transforms, we propose a flexible memory size that can be implemented in the design. To cope with different wavelet filters, we feature a multicontext configuration to select among various forward and inverse DWTs/DWPs. For the 16-bit implementation, the estimated area of the proposed wavelet processor with 8 PEs configuration and 2×2×512 words memory in a 0.18-μm technology is 2.5 mm square and the estimated operating frequency is 319 MHz.
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Christian Piguet; Ricardo Reis; Dimitrios Soudris. 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2008, Rhodes Island, India. Springer, IFIP Advances in Information and Communication Technology, AICT-313, pp.154-173, 2010, VLSI-SoC: Design Methodologies for SoC and SiP. 〈10.1007/978-3-642-12267-5_9〉
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Andre Guntoro, Manfred Glesner. A Lifting-Based Discrete Wavelet Transform and Discrete Wavelet Packet Processor with Support for Higher Order Wavelet Filters. Christian Piguet; Ricardo Reis; Dimitrios Soudris. 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2008, Rhodes Island, India. Springer, IFIP Advances in Information and Communication Technology, AICT-313, pp.154-173, 2010, VLSI-SoC: Design Methodologies for SoC and SiP. 〈10.1007/978-3-642-12267-5_9〉. 〈hal-01054539〉

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