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Chip-Size Evaluation of a Multithreaded Processor Enhanced with a PID Controller
Abstract : In this paper the additional chip size of a Proportional/Integral/Diff-erential (PID) controller in a multithreaded processor is evaluated. The task of the PID unit is to stabilize a thread's throughput, the instruction per cycle rate (IPC rate). The stabilization of the IPC rate allocated to the main thread increases the efficiency of the processor and also the execution time remaining for other threads. The overhead introduced by the PID controller implementation in the VHDL model of an embedded Java real-time-system is examined.
Cited literature [27 references]
https://hal.inria.fr/hal-01055381
Contributor : Hal Ifip <>
Submitted on : Tuesday, August 12, 2014 - 4:20:30 PM
Last modification on : Thursday, March 5, 2020 - 5:40:49 PM
Long-term archiving on: : Wednesday, November 26, 2014 - 11:06:34 PM
Contributor : Hal Ifip <>
Submitted on : Tuesday, August 12, 2014 - 4:20:30 PM
Last modification on : Thursday, March 5, 2020 - 5:40:49 PM
Long-term archiving on: : Wednesday, November 26, 2014 - 11:06:34 PM
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