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Chip-Size Evaluation of a Multithreaded Processor Enhanced with a PID Controller

Abstract : In this paper the additional chip size of a Proportional/Integral/Diff-erential (PID) controller in a multithreaded processor is evaluated. The task of the PID unit is to stabilize a thread's throughput, the instruction per cycle rate (IPC rate). The stabilization of the IPC rate allocated to the main thread increases the efficiency of the processor and also the execution time remaining for other threads. The overhead introduced by the PID controller implementation in the VHDL model of an embedded Java real-time-system is examined.
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Submitted on : Tuesday, August 12, 2014 - 4:20:30 PM
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Michael Bauer, Mathias Pacher, Uwe Brinkschulte. Chip-Size Evaluation of a Multithreaded Processor Enhanced with a PID Controller. 8th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems (SEUS), Oct 2010, Waidhofen/Ybbs, Austria. pp.3-12, ⟨10.1007/978-3-642-16256-5_3⟩. ⟨hal-01055381⟩



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